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公开(公告)号：US10916700B2
公开(公告)日：2021-02-09
申请号：US16513014
申请日：2019-07-16
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seul-ji Song , Sung-won Kim , Il-mok Park , Jong-chul Park , Ji-hyun Jeong
Abstract: A method of fabricating a memory device may include forming a first conductive line extending over a substrate in a first direction, forming a memory cell pillar on the first conductive line, and forming a second conductive line extending over the memory cell pillar in a second direction that intersects the first direction, such that the first and second conductive lines vertically overlap with the memory cell pillar interposed between the first and second conductive lines. The memory cell pillar may include a heating electrode layer and a resistive memory layer. The resistive memory layer may include a wedge memory portion and a body memory portion. The wedge memory portion may contact the heating electrode layer and may have a width that that changes with increasing distance from the heating electrode layer. The body memory portion may be connected to the wedge memory portion.
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公开(公告)号：US20200075674A1
公开(公告)日：2020-03-05
申请号：US16351969
申请日：2019-03-13
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seul-ji Song , Il-mok Park
Abstract: A memory device includes a lower conductive line, a first memory unit, a second memory unit, and a shared lower electrode including first and second portions electrically connecting respective ones of the first memory unit and the second memory unit to the lower conductive line. A first insulating region is disposed between the first and second memory units. A second insulating region is disposed on the first insulating region. The device further includes a first switch unit on the first memory unit and including an upper electrode with a portion protruding from the second insulating region and a second switch unit on the second memory unit and including an upper electrode with a portion protruding from the second insulating region. First and second upper conductive lines contact the protruding portions of the respective upper electrodes.
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公开(公告)号：US10700127B2
公开(公告)日：2020-06-30
申请号：US16433511
申请日：2019-06-06
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seul-ji Song , Jung-hoon Park , Sung-ho Eun
Abstract: A memory device includes first conductive lines extending on a substrate along a first direction; second conductive lines extending on the first conductive lines along a second direction intersecting with the first direction; and memory cell structures, which are at intersections between the first conductive lines and the second conductive lines and connected to the first conductive lines and the second conductive lines, each of the memory cell structures including a first electrode layer, a second electrode layer, and a resistive memory layer between the first electrode layer and the second electrode layer. A first sidewall of each of the resistive memory layers is sloped and has a horizontal width that decreases in a direction away from the substrate, and a second sidewall of each of the resistive memory layer adjacent to the first sidewall is sloped and has a horizontal width that increases in a direction away from the substrate.
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Patent Agency Ranking
公开(公告)号：US20190341547A1
公开(公告)日：2019-11-07
申请号：US16513014
申请日：2019-07-16
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seul-ji Song , Sung-won Kim , Il-mok Park , Jong-chul Park , Ji-hyun Jeong
Abstract: A memory device may include a first conductive line, a second conductive line extending in a direction intersecting the first conductive line, such that the first conductive line and the second conductive line vertically overlap at a cross-point between the first conductive line and the second conductive line, and a memory cell pillar at the cross-point. The memory cell pillar may include a heating electrode layer and a resistive memory layer contacting the heating electrode layer. The resistive memory layer may include a wedge memory portion having a width that increases continuously in proportion with increasing distance from the heating electrode layer, and a body memory portion connected to the wedge memory portion such that the body memory portion and the wedge memory portion comprise an individual and continuous layer, the body memory portion having a greater width than the wedge memory portion.
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公开(公告)号：US20190140021A1
公开(公告)日：2019-05-09
申请号：US16006314
申请日：2018-06-12
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seul-ji Song , Jung-hoon Park , Sung-ho Eun
CPC classification number: H01L27/2463 , H01L27/2427 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1683
Abstract: A memory device includes first conductive lines extending on a substrate along a first direction; second conductive lines extending on the first conductive lines along a second direction intersecting with the first direction; and memory cell structures, which are at intersections between the first conductive lines and the second conductive lines and connected to the first conductive lines and the second conductive lines, each of the memory cell structures including a first electrode layer, a second electrode layer, and a resistive memory layer between the first electrode layer and the second electrode layer. A first sidewall of each of the resistive memory layers is sloped and has a horizontal width that decreases in a direction away from the substrate, and a second sidewall of each of the resistive memory layer adjacent to the first sidewall is sloped and has a horizontal width that increases in a direction away from the substrate.
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公开(公告)号：US10686013B2
公开(公告)日：2020-06-16
申请号：US16351969
申请日：2019-03-13
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seul-ji Song , Il-mok Park
Abstract: A memory device includes a lower conductive line, a first memory unit, a second memory unit, and a shared lower electrode including first and second portions electrically connecting respective ones of the first memory unit and the second memory unit to the lower conductive line. A first insulating region is disposed between the first and second memory units. A second insulating region is disposed on the first insulating region. The device further includes a first switch unit on the first memory unit and including an upper electrode with a portion protruding from the second insulating region and a second switch unit on the second memory unit and including an upper electrode with a portion protruding from the second insulating region. First and second upper conductive lines contact the protruding portions of the respective upper electrodes.
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公开(公告)号：US10403817B2
公开(公告)日：2019-09-03
申请号：US15867951
申请日：2018-01-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seul-ji Song , Sung-won Kim , Il-mok Park , Jong-chul Park , Ji-Hyun Jeong
Abstract: A memory device may include a first conductive line, a second conductive line extending in a direction intersecting the first conductive line, such that the first conductive line and the second conductive line vertically overlap at a cross-point between the first conductive line and the second conductive line, and a memory cell pillar at the cross-point. The memory cell pillar may include a heating electrode layer and a resistive memory layer contacting the heating electrode layer. The resistive memory layer may include a wedge memory portion having a width that increases continuously in proportion with increasing distance from the heating electrode layer, and a body memory portion connected to the wedge memory portion such that the body memory portion and the wedge memory portion comprise an individual and continuous layer, the body memory portion having a greater width than the wedge memory portion.
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公开(公告)号：US10355050B2
公开(公告)日：2019-07-16
申请号：US16006314
申请日：2018-06-12
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seul-ji Song , Jung-hoon Park , Sung-ho Eun
Abstract: A memory device includes first conductive lines extending on a substrate along a first direction; second conductive lines extending on the first conductive lines along a second direction intersecting with the first direction; and memory cell structures, which are at intersections between the first conductive lines and the second conductive lines and connected to the first conductive lines and the second conductive lines, each of the memory cell structures including a first electrode layer, a second electrode layer, and a resistive memory layer between the first electrode layer and the second electrode layer. A first sidewall of each of the resistive memory layers is sloped and has a horizontal width that decreases in a direction away from the substrate, and a second sidewall of each of the resistive memory layer adjacent to the first sidewall is sloped and has a horizontal width that increases in a direction away from the substrate.
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