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公开(公告)号：US20190341547A1
公开(公告)日：2019-11-07
申请号：US16513014
申请日：2019-07-16
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seul-ji Song , Sung-won Kim , Il-mok Park , Jong-chul Park , Ji-hyun Jeong
Abstract: A memory device may include a first conductive line, a second conductive line extending in a direction intersecting the first conductive line, such that the first conductive line and the second conductive line vertically overlap at a cross-point between the first conductive line and the second conductive line, and a memory cell pillar at the cross-point. The memory cell pillar may include a heating electrode layer and a resistive memory layer contacting the heating electrode layer. The resistive memory layer may include a wedge memory portion having a width that increases continuously in proportion with increasing distance from the heating electrode layer, and a body memory portion connected to the wedge memory portion such that the body memory portion and the wedge memory portion comprise an individual and continuous layer, the body memory portion having a greater width than the wedge memory portion.
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公开(公告)号：US20190172502A1
公开(公告)日：2019-06-06
申请号：US16168153
申请日：2018-10-23
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ji-hyun Jeong , Jae-hyun Park
Abstract: A memory device includes a first cell block on a substrate at a first level, and a second cell block on the substrate at a second level different from the first level. Each of the first and second cell blocks includes a word line extending in a first direction that is parallel to a top surface of the substrate, a word line contact connected to a center point of the word line, a bit line extending in a second direction that is parallel to the top surface of the substrate and intersects the first direction, a bit line contact connected to a center point of the bit line, and a memory cell between the word and bit lines. The second cell block is offset from the first cell block in at least one of the first and second directions.
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公开(公告)号：US10263040B2
公开(公告)日：2019-04-16
申请号：US15906550
申请日：2018-02-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ji-hyun Jeong , Gwan-hyeob Koh , Dae-hwan Kang
IPC: H01L27/24 , H01L27/102 , H01L45/00 , H01L21/20 , G11C13/00
Abstract: A memory device includes a first electrode line layer including a plurality of first electrode lines extending on a substrate in a first direction and being spaced apart from each other, a second electrode line layer including a plurality of second electrode lines extending on the first electrode line layer in a second direction that is different from the first direction and being spaced apart from each other, and a memory cell layer including a plurality of first memory cells located at a plurality of intersections between the plurality of first electrode lines and the plurality of second electrode lines, each first memory cell including a selection device layer, an intermediate electrode and a variable resistance layer that are sequentially stacked. A side surface of the variable resistance layer is perpendicular to a top surface of the substrate or inclined to be gradually wider toward an upper portion of the variable resistance layer. The first memory cell has a side surface slope so as to have a width gradually decreasing toward its upper portion.
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公开(公告)号：US10923162B2
公开(公告)日：2021-02-16
申请号：US16869804
申请日：2020-05-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ji-hyun Jeong , Jae-hyun Park
Abstract: A memory device includes a first cell block on a substrate at a first level, and a second cell block on the substrate at a second level different from the first level. Each of the first and second cell blocks includes a word line extending in a first direction that is parallel to a top surface of the substrate, a word line contact connected to a center point of the word line, a bit line extending in a second direction that is parallel to the top surface of the substrate and intersects the first direction, a bit line contact connected to a center point of the bit line, and a memory cell between the word and bit lines. The second cell block is offset from the first cell block in at least one of the first and second directions.
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公开(公告)号：US10916700B2
公开(公告)日：2021-02-09
申请号：US16513014
申请日：2019-07-16
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seul-ji Song , Sung-won Kim , Il-mok Park , Jong-chul Park , Ji-hyun Jeong
Abstract: A method of fabricating a memory device may include forming a first conductive line extending over a substrate in a first direction, forming a memory cell pillar on the first conductive line, and forming a second conductive line extending over the memory cell pillar in a second direction that intersects the first direction, such that the first and second conductive lines vertically overlap with the memory cell pillar interposed between the first and second conductive lines. The memory cell pillar may include a heating electrode layer and a resistive memory layer. The resistive memory layer may include a wedge memory portion and a body memory portion. The wedge memory portion may contact the heating electrode layer and may have a width that that changes with increasing distance from the heating electrode layer. The body memory portion may be connected to the wedge memory portion.
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Patent Agency Ranking
公开(公告)号：US10685682B2
公开(公告)日：2020-06-16
申请号：US16168153
申请日：2018-10-23
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ji-hyun Jeong , Jae-hyun Park
Abstract: A memory device includes a first cell block on a substrate at a first level, and a second cell block on the substrate at a second level different from the first level. Each of the first and second cell blocks includes a word line extending in a first direction that is parallel to a top surface of the substrate, a word line contact connected to a center point of the word line, a bit line extending in a second direction that is parallel to the top surface of the substrate and intersects the first direction, a bit line contact connected to a center point of the bit line, and a memory cell between the word and bit lines. The second cell block is offset from the first cell block in at least one of the first and second directions.
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公开(公告)号：US09941333B2
公开(公告)日：2018-04-10
申请号：US15288233
申请日：2016-10-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ji-hyun Jeong , Gwan-hyeob Koh , Dae-hwan Kang
IPC: H01L27/082 , H01L27/24 , H01L29/12 , H01L45/00 , H01L27/102 , G11C13/00
CPC classification number: H01L27/2481 , G11C13/0004 , G11C13/0023 , G11C13/004 , G11C13/0069 , G11C2213/71 , G11C2213/72 , H01L27/1026 , H01L27/2427 , H01L27/2445 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1293 , H01L45/144 , H01L45/16 , H01L45/1675
Abstract: A memory device includes a first electrode line layer including a plurality of first electrode lines extending on a substrate in a first direction and being spaced apart from each other, a second electrode line layer including a plurality of second electrode lines extending on the first electrode line layer in a second direction that is different from the first direction and being spaced apart from each other, and a memory cell layer including a plurality of first memory cells located at a plurality of intersections between the plurality of first electrode lines and the plurality of second electrode lines, each first memory cell including a selection device layer, an intermediate electrode and a variable resistance layer that are sequentially stacked. A side surface of the variable resistance layer is perpendicular to a top surface of the substrate or inclined to be gradually wider toward an upper portion of the variable resistance layer. The first memory cell has a side surface slope so as to have a width gradually decreasing toward its upper portion.
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公开(公告)号：US11735231B2
公开(公告)日：2023-08-22
申请号：US17526155
申请日：2021-11-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ji-hyun Jeong , Jae-hyun Park
CPC classification number: G11C5/063 , G11C5/025 , G11C13/0023 , G11C13/0026 , G11C13/0028 , H10B61/10 , H10B61/22 , H10B63/24 , H10B63/84 , G11C2213/52 , G11C2213/71 , G11C2213/75 , H10N70/20 , H10N70/231 , H10N70/826 , H10N70/8413 , H10N70/8828 , H10N70/8833
Abstract: A memory device includes a first cell block on a substrate at a first level, and a second cell block on the substrate at a second level different from the first level. Each of the first and second cell blocks includes a word line extending in a first direction that is parallel to a top surface of the substrate, a word line contact connected to a center point of the word line, a bit line extending in a second direction that is parallel to the top surface of the substrate and intersects the first direction, a bit line contact connected to a center point of the bit line, and a memory cell between the word and bit lines. The second cell block is offset from the first cell block in at least one of the first and second directions.
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公开(公告)号：US11183538B2
公开(公告)日：2021-11-23
申请号：US16835667
申请日：2020-03-31
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ji-hyun Jeong , Gwan-hyeob Koh , Dae-hwan Kang
IPC: H01L27/24 , H01L27/102 , H01L45/00 , G11C13/00
Abstract: A memory device includes a first electrode line layer including a plurality of first electrode lines extending on a substrate in a first direction and being spaced apart from each other, a second electrode line layer including a plurality of second electrode lines extending on the first electrode line layer in a second direction that is different from the first direction and being spaced apart from each other, and a memory cell layer including a plurality of first memory cells located at a plurality of intersections between the plurality of first electrode lines and the plurality of second electrode lines, each first memory cell including a selection device layer, an intermediate electrode and a variable resistance layer that are sequentially stacked. A side surface of the variable resistance layer is perpendicular to a top surface of the substrate or inclined to be gradually wider toward an upper portion of the variable resistance layer. The first memory cell has a side surface slope so as to have a width gradually decreasing toward its upper portion.
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公开(公告)号：US11183223B2
公开(公告)日：2021-11-23
申请号：US17143340
申请日：2021-01-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ji-hyun Jeong , Jae-hyun Park
Abstract: A memory device includes a first cell block on a substrate at a first level, and a second cell block on the substrate at a second level different from the first level. Each of the first and second cell blocks includes a word line extending in a first direction that is parallel to a top surface of the substrate, a word line contact connected to a center point of the word line, a bit line extending in a second direction that is parallel to the top surface of the substrate and intersects the first direction, a bit line contact connected to a center point of the bit line, and a memory cell between the word and bit lines. The second cell block is offset from the first cell block in at least one of the first and second directions.
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