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公开(公告)号：US11201192B2
公开(公告)日：2021-12-14
申请号：US17030425
申请日：2020-09-24
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ji-Hyun Jeong , Gwan-hyeob Koh , Dae-hwan Kang
IPC: H01L27/24 , H01L27/102 , H01L45/00 , G11C13/00
Abstract: A memory device includes a first electrode line layer including a plurality of first electrode lines extending on a substrate in a first direction and being spaced apart from each other, a second electrode line layer including a plurality of second electrode lines extending on the first electrode line layer in a second direction that is different from the first direction and being spaced apart from each other, and a memory cell layer including a plurality of first memory cells located at a plurality of intersections between the plurality of first electrode lines and the plurality of second electrode lines, each first memory cell including a selection device layer, an intermediate electrode and a variable resistance layer that are sequentially stacked. A side surface of the variable resistance layer is perpendicular to a top surface of the substrate or inclined to be gradually wider toward an upper portion of the variable resistance layer. The first memory cell has a side surface slope so as to have a width gradually decreasing toward its upper portion.
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公开(公告)号：US09887354B2
公开(公告)日：2018-02-06
申请号：US15296423
申请日：2016-10-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Ji-Hyun Jeong , Jin-Woo Lee , Gwan-Hyeob Koh , Dae-Hwan Kang
CPC classification number: H01L45/144 , H01L27/2427 , H01L27/2463 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/141 , H01L45/16 , H01L45/1675 , H01L45/1683
Abstract: Provided are a memory device and a method of manufacturing the same. Memory cells of the memory device are formed separately from first electrode lines and second electrode lines, wherein the second electrode lines over the memory cells are formed by a damascene process, thereby avoiding complications associated with CMP being excessively or insufficiently performed on an insulation layer over the memory cells.
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公开(公告)号：US10923655B2
公开(公告)日：2021-02-16
申请号：US16726513
申请日：2019-12-24
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ji-Hyun Jeong , Ilmok Park , Si-Ho Song
Abstract: Disclosed are a variable resistance memory device and a method of manufacturing the same. The device comprises a first conductive line extending in a first direction, a second conductive line extending in a second direction intersecting the first direction, a memory cell at an intersection between the first conductive line and the second conductive line, a first electrode between the first conductive line and the memory cell, and a second electrode between the second conductive line and the memory cell. The memory cell comprises a switching pattern, an intermediate electrode, a first resistivity control pattern, and a variable resistance pattern that are connected in series between the first conductive line and the second conductive line. Resistivity of the first resistivity control pattern is less than resistivity of the second electrode.
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公开(公告)号：US10566529B2
公开(公告)日：2020-02-18
申请号：US15862926
申请日：2018-01-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Ji-Hyun Jeong , Jin-Woo Lee , Gwan-Hyeob Koh , Dae-Hwan Kang
Abstract: Provided are a memory device and a method of manufacturing the same. Memory cells of the memory device are formed separately from first electrode lines and second electrode lines, wherein the second electrode lines over the memory cells are formed by a damascene process, thereby avoiding complications associated with CMP being excessively or insufficiently performed on an insulation layer over the memory cells.
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公开(公告)号：US10403817B2
公开(公告)日：2019-09-03
申请号：US15867951
申请日：2018-01-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seul-ji Song , Sung-won Kim , Il-mok Park , Jong-chul Park , Ji-Hyun Jeong
Abstract: A memory device may include a first conductive line, a second conductive line extending in a direction intersecting the first conductive line, such that the first conductive line and the second conductive line vertically overlap at a cross-point between the first conductive line and the second conductive line, and a memory cell pillar at the cross-point. The memory cell pillar may include a heating electrode layer and a resistive memory layer contacting the heating electrode layer. The resistive memory layer may include a wedge memory portion having a width that increases continuously in proportion with increasing distance from the heating electrode layer, and a body memory portion connected to the wedge memory portion such that the body memory portion and the wedge memory portion comprise an individual and continuous layer, the body memory portion having a greater width than the wedge memory portion.
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Patent Agency Ranking
公开(公告)号：US11349074B2
公开(公告)日：2022-05-31
申请号：US17009004
申请日：2020-09-01
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Ji-Hyun Jeong , Jin-Woo Lee , Gwan-Hyeob Koh , Dae-Hwan Kang
Abstract: Provided are a memory device and a method of manufacturing the same. Memory cells of the memory device are formed separately from first electrode lines and second electrode lines, wherein the second electrode lines over the memory cells are formed by a damascene process, thereby avoiding complications associated with CMP being excessively or insufficiently performed on an insulation layer over the memory cells.
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公开(公告)号：US10804466B2
公开(公告)日：2020-10-13
申请号：US16743594
申请日：2020-01-15
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Ji-Hyun Jeong , Jin-Woo Lee , Gwan-Hyeob Koh , Dae-Hwan Kang
Abstract: Provided are a memory device and a method of manufacturing the same. Memory cells of the memory device are formed separately from first electrode lines and second electrode lines, wherein the second electrode lines over the memory cells are formed by a damascene process, thereby avoiding complications associated with CMP being excessively or insufficiently performed on an insulation layer over the memory cells.
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公开(公告)号：US10566386B2
公开(公告)日：2020-02-18
申请号：US15990913
申请日：2018-05-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ji-Hyun Jeong
Abstract: A method of manufacturing a variable memory device includes forming a switching layer on a first conductive layer, forming a heating layer on the switching layer, the heating layer extending in a first direction, performing a first patterning process on the first conductive layer, the switching layer, and the heating layer to form a first trench extending in a second direction intersecting the first direction, forming variable resistance patterns on the heating layer, forming a second conductive layer on the variable resistance patterns, and performing a second patterning process on the switching layer, the heating layer, and the second conductive layer to form a second trench extending in the first direction and being between the variable resistance patterns.
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公开(公告)号：US10547000B2
公开(公告)日：2020-01-28
申请号：US16014871
申请日：2018-06-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ji-Hyun Jeong , Ilmok Park , Si-Ho Song
Abstract: Disclosed are a variable resistance memory device and a method of manufacturing the same. The device comprises a first conductive line extending in a first direction, a second conductive line extending in a second direction intersecting the first direction, a memory cell at an intersection between the first conductive line and the second conductive line, a first electrode between the first conductive line and the memory cell, and a second electrode between the second conductive line and the memory cell. The memory cell comprises a switching pattern, an intermediate electrode, a first resistivity control pattern, and a variable resistance pattern that are connected in series between the first conductive line and the second conductive line. Resistivity of the first resistivity control pattern is less than resistivity of the second electrode.
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公开(公告)号：US20190019950A1
公开(公告)日：2019-01-17
申请号：US15869892
申请日：2018-01-12
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sungwon Kim , Sung-Ho Eun , Ilmok Park , Junghoon Park , Seulji Song , Ji-Hyun Jeong
CPC classification number: H01L45/1675 , G11C13/0004 , G11C13/0026 , G11C13/0028 , G11C2213/31 , G11C2213/76 , H01L27/2427 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/122 , H01L45/1233 , H01L45/1273 , H01L45/141 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/1683 , H01L45/1691
Abstract: Variable resistance memory devices and methods of forming the same are provided. The variable resistance memory devices may include a substrate including a cell region and a peripheral region, first conductive lines on the substrate, second conductive lines traversing the first conductive lines, variable resistance structures at intersecting points of the first conductive lines and the second conductive lines, and bottom electrodes between the first conductive lines and the variable resistance structures. The cell region may include a boundary region contacting the peripheral region, and one of the first conductive lines is electrically insulated from one of the variable resistance structures that is on the boundary region and overlaps the one of the first conductive lines,
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