公开(公告)号：US11037829B2

公开(公告)日：2021-06-15

申请号：US16460127

申请日：2019-07-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Hyun Lee ,  Jeong Yun Lee ,  Seung Ju Park ,  Geum Jung Seong ,  Young Mook Oh ,  Seung Soo Hong

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/417 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device capable of improving operation performance and reliability, may include a gate insulating support to isolate gate electrodes that are adjacent in a length direction. The semiconductor device includes a first gate structure on a substrate, the first gate structure extending lengthwise in a first direction to have two long sides and two short sides, relative to each other, and including a first gate spacer; a second gate structure on the substrate, the second gate structure extending lengthwise in the first direction to have two long sides and two short sides, relative to each other, and including a second gate spacer, wherein a first short side of the second gate structure faces a first short side of the first gate structure; and a gate insulating support disposed between the first short side of the first gate structure and the first short side of the second gate structure and extending lengthwise in a second direction different from the first direction, a length of the gate insulating support in the second direction being greater than a width of each of the first gate structure and the second gate structure in the second direction.

公开(公告)号：US12125750B2

公开(公告)日：2024-10-22

申请号：US18118505

申请日：2023-03-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Hyun Lee ,  Jeong Yun Lee ,  Seung Ju Park ,  Geum Jung Seong ,  Young Mook Oh ,  Seung Soo Hong

IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L21/823462 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823821 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/42364 ,  H01L29/785 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/6656

Abstract: A semiconductor device capable of improving operation performance and reliability, may include a gate insulating support to isolate gate electrodes that are adjacent in a length direction. The semiconductor device includes a first gate structure on a substrate, the first gate structure extending lengthwise in a first direction to have two long sides and two short sides, relative to each other, and including a first gate spacer; a second gate structure on the substrate, the second gate structure extending lengthwise in the first direction to have two long sides and two short sides, relative to each other, and including a second gate spacer, wherein a first short side of the second gate structure faces a first short side of the first gate structure; and a gate insulating support disposed between the first short side of the first gate structure and the first short side of the second gate structure and extending lengthwise in a second direction different from the first direction, a length of the gate insulating support in the second direction being greater than a width of each of the first gate structure and the second gate structure in the second direction.

公开(公告)号：US11621196B2

公开(公告)日：2023-04-04

申请号：US17328348

申请日：2021-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Hyun Lee ,  Jeong Yun Lee ,  Seung Ju Park ,  Geum Jung Seong ,  Young Mook Oh ,  Seung Soo Hong

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/417 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device capable of improving operation performance and reliability, may include a gate insulating support to isolate gate electrodes that are adjacent in a length direction. The semiconductor device includes a first gate structure on a substrate, the first gate structure extending lengthwise in a first direction to have two long sides and two short sides, relative to each other, and including a first gate spacer; a second gate structure on the substrate, the second gate structure extending lengthwise in the first direction to have two long sides and two short sides, relative to each other, and including a second gate spacer, wherein a first short side of the second gate structure faces a first short side of the first gate structure; and a gate insulating support disposed between the first short side of the first gate structure and the first short side of the second gate structure and extending lengthwise in a second direction different from the first direction, a length of the gate insulating support in the second direction being greater than a width of each of the first gate structure and the second gate structure in the second direction.

公开(公告)号：US10395990B2

公开(公告)日：2019-08-27

申请号：US15718482

申请日：2017-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Hyun Lee ,  Jeong Yun Lee ,  Seung Ju Park ,  Geum Jung Seong ,  Young Mook Oh ,  Seung Soo Hong

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/66 ,  H01L27/088

Abstract: A semiconductor device capable of improving operation performance and reliability, may include a gate insulating support to isolate gate electrodes that are adjacent in a length direction. The semiconductor device includes a first gate structure on a substrate, the first gate structure extending lengthwise in a first direction to have two long sides and two short sides, relative to each other, and including a first gate spacer; a second gate structure on the substrate, the second gate structure extending lengthwise in the first direction to have two long sides and two short sides, relative to each other, and including a second gate spacer, wherein a first short side of the second gate structure faces a first short side of the first gate structure; and a gate insulating support disposed between the first short side of the first gate structure and the first short side of the second gate structure and extending lengthwise in a second direction different from the first direction, a length of the gate insulating support in the second direction being greater than a width of each of the first gate structure and the second gate structure in the second direction.

公开(公告)号：US10002967B2

公开(公告)日：2018-06-19

申请号：US15602131

申请日：2017-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Soo Hong ,  Jeong Yun Lee ,  Kyung Seok Min ,  Seung Ju Park ,  Geum Jung Seong ,  Bo Ra Lim

IPC: H01L21/70 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/7855 ,  H01L29/0611 ,  H01L29/0657 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7854

Abstract: Semiconductor devices as described herein may include a fin-shaped pattern extending in a first direction, first and second side walls facing each other, first and second gate electrodes extending in a second direction and spaced apart from each other, a first gate spacer that is on a side wall of the first gate electrode, a second gate spacer that is on a side wall of the second gate electrode, a first trench in the fin-shaped pattern that is between the first and second gate electrodes and having a first width, and a second trench in the fin-shaped pattern that is below the first trench and has a second width smaller than the first width. The fin-shaped pattern may include first and second inflection points on the side walls of the fin-shaped pattern, and a bottom surface of the second trench may be lower than the inflection points.

公开(公告)号：US20180069125A1

公开(公告)日：2018-03-08

申请号：US15602131

申请日：2017-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Soo Hong ,  Jeong Yun Lee ,  Kyung Seok Min ,  Seung Ju Park ,  Geum Jung Seong ,  Bo Ra Lim

IPC: H01L29/78 ,  H01L29/06

CPC classification number: H01L29/7855 ,  H01L29/0611 ,  H01L29/0657 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7854

Abstract: Semiconductor devices as described herein may include a fin-shaped pattern extending in a first direction, first and second side walls facing each other, first and second gate electrodes extending in a second direction and spaced apart from each other, a first gate spacer that is on a side wall of the first gate electrode, a second gate spacer that is on a side wall of the second gate electrode, a first trench in the fin-shaped pattern that is between the first and second gate electrodes and having a first width, and a second trench in the fin-shaped pattern that is below the first trench and has a second width smaller than the first width. The fin-shaped pattern may include first and second inflection points on the side walls of the fin-shaped pattern, and a bottom surface of the second trench may be lower than the inflection points.

公开(公告)号：US09876013B1

公开(公告)日：2018-01-23

申请号：US15477554

申请日：2017-04-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Ju Park ,  Jeong Yun Lee ,  Kyung Seok Min ,  Geum Jung Seong ,  Bo Ra Lim ,  Seung Soo Hong

IPC: H01L23/48 ,  H01L27/088 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823468 ,  H01L29/42356 ,  H01L29/66545

Abstract: A semiconductor device is provided including first and second active fin arrays on a substrate. The semiconductor device further includes a pair of first gate spacers disposed on the first and second active fin arrays, each of the pair of first gate spacers including a first region having a first width, a second region having a second width, and a third region between the first region and the second region and having a third width; and first and second gate electrodes, the first gate electrode disposed between the first regions and the second gate electrode disposed between the second regions. The first regions are on the first active fin array, the second regions are on the second active fin array, and the third regions are between the first active fin array and the second active fin array. Each of the first and second widths is greater than the third width.

公开(公告)号：US09741854B2

公开(公告)日：2017-08-22

申请号：US14959457

申请日：2015-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keun Hee Bai ,  Kyoung Hwan Yeo ,  Seung Seok Ha ,  Seung Ju Park ,  Do Hyoung Kim ,  Myeong Cheol Kim ,  Jae Hyoung Koo ,  Ki Byung Park

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66818 ,  H01L29/7851

Abstract: There is provided a method for manufacturing a semiconductor device including a substrate including a plurality of active regions, a plurality of gate electrodes extending in a first direction to intersect a portion of the plurality of active regions, and including first and second gate electrodes disposed to be adjacent to each other in the first direction, a gate isolation portion disposed between the first and second gate electrodes. The gate isolation portion includes a first layer and second layers disposed on both ends of the first layer in a second direction perpendicular to the first direction.