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公开(公告)号：US20150331719A1
公开(公告)日：2015-11-19
申请号：US14800002
申请日：2015-07-15
Inventor： Woong SEO , Yeon-Gon CHO , Soo-Jung RYU , Seok-Woo SONG , JOHN Dongjun KIM , Min-Seok LEE
IPC: G06F9/50
CPC classification number: G06F9/505 , G06F9/46 , G06F9/4881 , G06F2209/5022
Abstract: An apparatus and a job scheduling method are provided. For example, the apparatus is a multi-core processing apparatus. The apparatus and method minimize performance degradation of a core caused by sharing resources by dynamically managing a maximum number of jobs assigned to each core of the apparatus. The apparatus includes at least one core including an active cycle counting unit configured to store a number of active cycles and a stall cycle counting unit configured to store a number of stall cycles and a job scheduler configured to assign at least one job to each of the at least one core, based on the number of active cycles and the number of stall cycles. When the ratio of the number of stall cycles to a number of active cycles for a core is too great, the job scheduler assigns fewer jobs to that core to improve performance.
Abstract translation: 提供了一种装置和作业调度方法。 例如，该装置是多核处理装置。 该装置和方法通过动态地管理分配给设备的每个核心的最大数量的作业来最小化共享资源所引起的核心性能下降。 所述设备包括至少一个核心，其包括被配置为存储多个活动周期的活动周期计数单元和被配置为存储多个失速周期的失速循环计数单元，以及作业调度器，其被配置为将至少一个作业分配给 至少一个核心，基于活动周期的数量和失速周期的数量。 当停顿周期数与核心的活动周期数之比太大时，作业调度程序为该核心分配较少的作业以提高性能。
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公开(公告)号：US20150143383A1
公开(公告)日：2015-05-21
申请号：US14606395
申请日：2015-01-27
Inventor： Woong SEO , Yeon-Gon CHO , Soo-Jung RYU , Seok-Woo SONG , JOHN Dongjun KIM , Min-Seok LEE
IPC: G06F9/50
CPC classification number: G06F9/505 , G06F9/46 , G06F9/4881 , G06F2209/5022
Abstract: An apparatus and a job scheduling method are provided. For example, the apparatus is a multi-core processing apparatus. The apparatus and method minimize performance degradation of a core caused by sharing resources by dynamically managing a maximum number of jobs assigned to each core of the apparatus. The apparatus includes at least one core including an active cycle counting unit configured to store a number of active cycles and a stall cycle counting unit configured to store a number of stall cycles and a job scheduler configured to assign at least one job to each of the at least one core, based on the number of active cycles and the number of stall cycles. When the ratio of the number of stall cycles to a number of active cycles for a core is too great, the job scheduler assigns fewer jobs to that core to improve performance.
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3.发明申请PROCESSOR CAPABLE OF SUPPORTING MULTIMODE AND MULTIMODE SUPPORTING METHOD THEREOF 审中-公开支持多模和多模支持方法的处理器公开(公告)号：US20150143081A1
公开(公告)日：2015-05-21
申请号：US14606240
申请日：2015-01-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Woong SEO , Yeon-Gon CHO , Soo-Jung RYU
CPC classification number: G06F15/8015 , G06F9/30058 , G06F9/3804 , G06F9/3851 , G06F9/3887 , G06F9/3889
Abstract: Embodiments include a processor capable of supporting multi-mode and corresponding methods. The processor includes front end units, a number of processing elements more than a number of the front end units; and a controller configured to determine if thread divergence occurs due to conditional branching. If there is thread divergence, the processor may set control information to control processing elements using currently activated front end units. If there is not, the processor may set control information to control processing elements using a currently activated front end unit.
Abstract translation: 实施例包括能够支持多模式和相应方法的处理器。 处理器包括前端单元，多个前端单元的多个处理元件; 以及控制器，被配置为确定是否由于条件分支而发生线程发散。 如果存在线程发散，则处理器可以设置控制信息以使用当前激活的前端单元来控制处理元件。 如果没有，则处理器可以使用当前激活的前端单元来设置控制信息以控制处理元件。
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公开(公告)号：US20140317388A1
公开(公告)日：2014-10-23
申请号：US14258622
申请日：2014-04-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Moo-Kyoung CHUNG , Soo-Jung RYU , Yeon-Gon CHO
IPC: G06F9/30
CPC classification number: G06F9/30145
Abstract: An apparatus and method for supporting a multi-mode. The apparatus for supporting a multi-mode may include an instruction distributor configured to select, according to a current execution mode, at least one instruction from among a plurality of received instructions that each include an operand and an opcode, and transfer the opcode included in each of at least one selected instruction to the plurality of functional units; an operand switch controller configured to generate, based on the operand included in each of the selected at least one instruction, switch configuration information for routing in order to execute the selected at least one instruction; and an operand switch configured to route, based on the switch configuration information, a functional unit output or a register file output to either a functional unit input or a register file input.
Abstract translation: 一种用于支持多模式的装置和方法。 用于支持多模式的装置可以包括指示分配器，其被配置为根据当前执行模式，从多个接收到的指令中选择每个包括操作数和操作码的至少一个指令，并且将包括在其中的操作码 对所述多个功能单元中的至少一个选择指令中的每一个; 操作数开关控制器，被配置为基于包括在所选择的至少一个指令中的每一个中的操作数来生成用于路由的交换配置信息，以执行所选择的至少一个指令; 以及操作数开关，被配置为基于所述开关配置信息将输出的功能单元输出或寄存器文件路由到功能单元输入或寄存器文件输入。
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公开(公告)号：US20150227490A1
公开(公告)日：2015-08-13
申请号：US14694420
申请日：2015-04-23
Inventor： Woong SEO , Han-Joon KIM , John KIM , Soo-Jung RYU
CPC classification number: G06F15/80 , G06F9/44505 , G06F15/17312 , H04L45/06 , H04L45/60
Abstract: Provided is a processor with a data transfer structure that is excellent in performance and efficiency. According to an aspect, the processor may include a plurality of processing elements, a plurality of routers respectively connected to the processing elements, and a plurality of connection links formed between the routers such that data is transferred between the processors via a network.
Abstract translation: 提供了具有优异性能和效率的数据传输结构的处理器。 根据一个方面，处理器可以包括多个处理元件，分别连接到处理元件的多个路由器，以及形成在路由器之间的多个连接链路，使得数据经由网络在处理器之间传送。
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Patent Agency Ranking
6.发明申请PROCESSOR FOR BATCH THREAD PROCESSING, BATCH THREAD PROCESSING METHOD USING THE SAME, AND CODE GENERATION APPARATUS FOR BATCH THREAD PROCESSING 审中-公开用于批量螺纹加工的处理器，使用其的批量螺纹加工方法以及用于批量螺纹加工的代码生成装置公开(公告)号：US20140317626A1
公开(公告)日：2014-10-23
申请号：US14258336
申请日：2014-04-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Moo-Kyoung CHUNG , Soo-Jung RYU , Yeon-Gon CHO
IPC: G06F9/46
CPC classification number: G06F9/466 , G06F8/45 , G06F9/3836 , G06F9/3851 , G06F9/3853 , G06F9/3887 , G06F9/3891
Abstract: A processor for batch thread processing includes a central register file, and one or more function unit batches each including two or more function units and one or more ports to access the central register file. The function units of the function unit batches execute an instruction batch including one or more instructions to sequentially execute the one or more instructions in the instruction batch.
Abstract translation: 用于批处理线程处理的处理器包括中央寄存器文件和一个或多个功能单元批次，每个功能单元批次包括两个或多个功能单元和一个或多个端口以访问中央寄存器文件。 功能单元批次的功能单元执行包括一个或多个指令的指令批次，以顺序执行指令批次中的一个或多个指令。
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公开(公告)号：US20130336587A1
公开(公告)日：2013-12-19
申请号：US13919384
申请日：2013-06-17
Inventor： Sang-Heon LEE , Soo-Jung RYU , Yeon-Gon CHO , Do-Hyun KIM , Yeong-Gil SHIN , Byeong-Hun LEE
IPC: G06T7/00
CPC classification number: G06T7/0081 , G06T7/11 , G06T2207/10081
Abstract: A region growing apparatus using multi-core includes a plurality of cores, each core including an operation controller configured to perform an operation for region growing of a 2D pixel region or 3D pixel region and an inner memory configured to store a queue associated with a seed pixel as a target of the operation; and a shared memory connected to the plurality of cores over a network and shared by the plurality of cores.
Abstract translation: 使用多核的区域生长装置包括多个核心，每个核心包括被配置为执行2D像素区域或3D像素区域的区域生长的操作的操作控制器和被配置为存储与种子相关联的队列的内部存储器 像素作为操作的目标; 以及通过网络连接到所述多个核并由所述多个核共享的共享存储器。
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8.发明申请CACHE CONTROL DEVICE FOR PREFETCHING AND PREFETCHING METHOD USING CACHE CONTROL DEVICE 有权用于使用高速缓存控制设备的前缀和前缀方法的缓存控制设备公开(公告)号：US20160055089A1
公开(公告)日：2016-02-25
申请号：US14931019
申请日：2015-11-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jun-Kyoung KIM , Dong-Hoon YOO , Jeong-Wook KIM , Soo-Jung RYU
IPC: G06F12/08
CPC classification number: G06F12/0862 , G06F8/4442 , G06F9/383 , G06F12/0875 , G06F2212/452 , G06F2212/6026 , G06F2212/6028
Abstract: The present examples relate to prefetching, and to a cache control device for prefetching and a prefetching method using the cache control device, wherein the cache control device analyzes a memory access pattern of program code, inserts, into the program code, a prefetching command generated by encoding the analyzed access pattern, and executes the prefetching command inserted into the program code in order to prefetch data into a cache, thereby maximizing prefetching efficiency.
Abstract translation: 本示例涉及预取，以及用于预取的高速缓存控制设备和使用高速缓存控制设备的预取方法，其中，高速缓存控制设备分析程序代码的存储器访问模式，将程序代码插入到生成的预取命令中 通过对所分析的访问模式进行编码，并且执行插入到程序代码中的预取命令，以便将数据预取到高速缓存中，从而最大化预取效率。
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9.发明申请PROCESSOR CAPABLE OF SUPPORTING MULTIMODE AND MULTIMODE SUPPORTING METHOD THEREOF 审中-公开支持多模和多模支持方法的处理器公开(公告)号：US20140215193A1
公开(公告)日：2014-07-31
申请号：US14165881
申请日：2014-01-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Woong SEO , Yeon-Gon CHO , Soo-Jung RYU
IPC: G06F9/30
CPC classification number: G06F15/8015 , G06F9/30058 , G06F9/3804 , G06F9/3851 , G06F9/3887 , G06F9/3889
Abstract: Embodiments include a processor capable of supporting multi-mode and corresponding methods. The processor includes front end units, a number of processing elements more than a number of the front end units; and a controller configured to determine if thread divergence occurs due to conditional branching. If there is thread divergence, the processor may set control information to control processing elements using currently activated front end units. If there is not, the processor may set control information to control processing elements using a currently activated front end unit.
Abstract translation: 实施例包括能够支持多模式和相应方法的处理器。 处理器包括前端单元，多个前端单元的多个处理元件; 以及控制器，被配置为确定是否由于条件分支而发生线程发散。 如果存在线程发散，则处理器可以设置控制信息以使用当前激活的前端单元来控制处理元件。 如果没有，则处理器可以使用当前激活的前端单元来设置控制信息以控制处理元件。
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10.发明申请METHOD OF COMPILING PROGRAM TO BE EXECUTED ON MULTI-CORE PROCESSOR, AND TASK MAPPING METHOD AND TASK SCHEDULING METHOD OF RECONFIGURABLE PROCESSOR 有权在多核处理器上执行程序的编译方法以及可重构处理器的任务映射方法和任务调度方法公开(公告)号：US20140109069A1
公开(公告)日：2014-04-17
申请号：US14051910
申请日：2013-10-11
Inventor： Jin-Hoo LEE , Moo-Kyoung CHUNG , Key-Young CHOI , Yeon-Gon CHO , Soo-Jung RYU
IPC: G06F9/45
Abstract: A method of compiling a program to be executed on a multicore processor is provided. The method may include generating an initial solution by mapping a task to a source processing element (PE) and a destination PE, and selecting a communication scheme for transmission of the task from the source PE to the destination PE, approximately optimizing the mapping and communication scheme included in the initial solution, and scheduling the task, wherein the communication scheme is designated in a compiling process.
Abstract translation: 提供了一种编译要在多核处理器上执行的程序的方法。 该方法可以包括通过将任务映射到源处理单元（PE）和目的地PE来生成初始解决方案，并且从源PE到目的地PE选择用于传输任务的通信方案，大致优化映射和通信 包括在初始解决方案中，并且调度任务，其中在编译过程中指定通信方案。
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