公开(公告)号：US09496336B2

公开(公告)日：2016-11-15

申请号：US14750027

申请日：2015-06-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soo-ho Shin ,  Yong-sung Kim ,  Tae-young Chung

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L27/088

CPC classification number: H01L21/28123 ,  H01L21/76224 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/10826 ,  H01L27/10879 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/4238 ,  H01L29/66795 ,  H01L29/7802 ,  H01L29/7827 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7853

Abstract: A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The device includes gate electrodes formed on element isolation layers that are disposed between active regions and have top surfaces that are higher than the top surfaces of the active regions. Since the gate electrodes are formed on the element isolation layers, leakage current in a semiconductor substrate is prevented. In addition, the gate electrodes are formed using a striped shape mask pattern, thereby obtaining a sufficient overlap margin compared to a contact shape or bar shape pattern.

公开(公告)号：US20150318350A1

公开(公告)日：2015-11-05

申请号：US14750027

申请日：2015-06-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soo-ho Shin ,  Yong-sung Kim ,  Tae-young Chung

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L21/28123 ,  H01L21/76224 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/10826 ,  H01L27/10879 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/4238 ,  H01L29/66795 ,  H01L29/7802 ,  H01L29/7827 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7853

Abstract: A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The device includes gate electrodes formed on element isolation layers that are disposed between active regions and have top surfaces that are higher than the top surfaces of the active regions. Since the gate electrodes are formed on the element isolation layers, leakage current in a semiconductor substrate is prevented. In addition, the gate electrodes are formed using a striped shape mask pattern, thereby obtaining a sufficient overlap margin compared to a contact shape or bar shape pattern.

公开(公告)号：US09966267B2

公开(公告)日：2018-05-08

申请号：US15292884

申请日：2016-10-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soo-ho Shin ,  Yong-sung Kim ,  Tae-young Chung

IPC: H01L29/78 ,  H01L21/28 ,  H01L27/088 ,  H01L29/66 ,  H01L29/06 ,  H01L21/762 ,  H01L29/423 ,  H01L27/108

CPC classification number: H01L21/28123 ,  H01L21/76224 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/10826 ,  H01L27/10879 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/4238 ,  H01L29/66795 ,  H01L29/7802 ,  H01L29/7827 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7853

Abstract: A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The device includes gate electrodes formed on element isolation layers that are disposed between active regions and have top surfaces that are higher than the top surfaces of the active regions. Since the gate electrodes are formed on the element isolation layers, leakage current in a semiconductor substrate is prevented. In addition, the gate electrodes are formed using a striped shape mask pattern, thereby obtaining a sufficient overlap margin compared to a contact shape or bar shape pattern.

公开(公告)号：US08873277B2

公开(公告)日：2014-10-28

申请号：US13648300

申请日：2012-10-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeoung-won Seo ,  Soo-ho Shin ,  Won-woo Lee ,  Jeong-soo Park ,  Young-yong Byun ,  Seong-jin Jang ,  Sang-woong Shin

IPC: G11C7/00 ,  G11C11/4091 ,  G11C8/14 ,  G11C11/4094 ,  G11C7/12

CPC classification number: G11C8/14 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4094 ,  G11C2207/005

Abstract: A semiconductor memory device includes a plurality of memory cell blocks including a first memory cell block having bit lines, an edge sense amplifier block including edge sense amplifiers coupled to a portion of the bit lines of the first memory cell block, and a balancing capacitor unit coupled to the edge sense amplifiers.

Abstract translation: 半导体存储器件包括多个存储单元块，它们包括具有位线的第一存储单元块，边沿读出放大器块，其包括耦合到第一存储单元块的位线的一部分的边沿读出放大器，以及平衡电容器单元 耦合到边缘读出放大器。