公开(公告)号：US10367002B2

公开(公告)日：2019-07-30

申请号：US15288517

申请日：2016-10-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Il Chang ,  Jun-Hee Lim ,  Yong-Seok Kim ,  Tae-Young Kim ,  Jae-Sung Sim ,  Su-Jin Ahn ,  Ji-Yeong Hwang

IPC: H01L27/11582 ,  H01L27/11578 ,  H01L29/66 ,  H01L21/265 ,  H01L27/11556 ,  H01L29/78 ,  H01L27/1157

Abstract: In a method of manufacturing a vertical semiconductor device, an insulation layer and a sacrificial layer are alternatively and repeatedly formed on a substrate to define a structure. The structure is etched to form a hole therethrough that exposes the substrate. A first semiconductor pattern is formed in a lower portion of the hole, and a blocking pattern, a charge storage pattern, a tunnel insulation pattern and a first channel pattern are formed on a sidewall of the hole. A second channel pattern is formed on the first channel pattern and the semiconductor pattern, and a second semiconductor pattern is formed on a portion of the second channel pattern on the semiconductor pattern to define an upper channel pattern including the second channel pattern and the second semiconductor pattern. The sacrificial layers are replaced with a plurality of gates, respectively, including a conductive material.

公开(公告)号：US11889692B2

公开(公告)日：2024-01-30

申请号：US17349193

申请日：2021-06-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chang-Min Choi ,  Ju-Young Lim ,  Su-Jin Ahn

IPC: H01L27/06 ,  H10B43/27 ,  H10B41/27 ,  H10B43/10 ,  H10B43/20 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50 ,  H01L23/528

CPC classification number: H10B43/27 ,  H01L23/5283 ,  H01L27/0688 ,  H10B41/27 ,  H10B43/10 ,  H10B43/20 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50

Abstract: A vertical memory device includes a substrate, a plurality of channels extending in a first direction substantially vertical to a top surface of the substrate, a plurality of gate lines surrounding a predetermined number of channels from among the channels, a plurality of common wirings electrically connected to the gate lines, and a plurality of signal wirings electrically connected to the gate lines via the common wirings. The gate lines are arranged and spaced apart from one another along the first direction. Each common wiring is electrically connected to a corresponding gate line at a same level of the corresponding gate line via a corresponding contact.

公开(公告)号：US20200312878A1

公开(公告)日：2020-10-01

申请号：US16903070

申请日：2020-06-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-il CHANG ,  Jun-Hee Lim ,  Yong-Seok Kim ,  Tae-Young Kim ,  Jae-Sung Sim ,  Su-Jin Ahn ,  Ji-Yeong Hwang

IPC: H01L27/11582 ,  H01L27/11578 ,  H01L29/66 ,  H01L29/78 ,  H01L27/1157 ,  H01L21/265 ,  H01L27/11556

Abstract: In a method of manufacturing a vertical semiconductor device, an insulation layer and a sacrificial layer are alternatively and repeatedly formed on a substrate to define a structure. The structure is etched to form a hole therethrough that exposes the substrate. A first semiconductor pattern is formed in a lower portion of the hole, and a blocking pattern, a charge storage pattern, a tunnel insulation pattern and a first channel pattern are formed on a sidewall of the hole. A second channel pattern is formed on the first channel pattern and the semiconductor pattern, and a second semiconductor pattern is formed on a portion of the second channel pattern on the semiconductor pattern to define an upper channel pattern including the second channel pattern and the second semiconductor pattern. The sacrificial layers are replaced with a plurality of gates, respectively, including a conductive material.

公开(公告)号：US11152390B2

公开(公告)日：2021-10-19

申请号：US16903070

申请日：2020-06-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Il Chang ,  Jun-Hee Lim ,  Yong-Seok Kim ,  Tae-Young Kim ,  Jae-Sung Sim ,  Su-Jin Ahn ,  Ji-Yeong Hwang

IPC: H01L27/11582 ,  H01L27/11578 ,  H01L29/66 ,  H01L29/78 ,  H01L27/1157 ,  H01L21/265 ,  H01L27/11556

Abstract: In a method of manufacturing a vertical semiconductor device, an insulation layer and a sacrificial layer are alternatively and repeatedly formed on a substrate to define a structure. The structure is etched to form a hole therethrough that exposes the substrate. A first semiconductor pattern is formed in a lower portion of the hole, and a blocking pattern, a charge storage pattern, a tunnel insulation pattern and a first channel pattern are formed on a sidewall of the hole. A second channel pattern is formed on the first channel pattern and the semiconductor pattern, and a second semiconductor pattern is formed on a portion of the second channel pattern on the semiconductor pattern to define an upper channel pattern including the second channel pattern and the second semiconductor pattern. The sacrificial layers are replaced with a plurality of gates, respectively, including a conductive material.

公开(公告)号：US10700092B2

公开(公告)日：2020-06-30

申请号：US16441163

申请日：2019-06-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Il Chang ,  Jun-Hee Lim ,  Yong-Seok Kim ,  Tae-Young Kim ,  Jae-Sung Sim ,  Su-Jin Ahn ,  Ji-Yeong Hwang

IPC: H01L27/11582 ,  H01L27/11578 ,  H01L29/66 ,  H01L29/78 ,  H01L27/1157 ,  H01L21/265 ,  H01L27/11556

Abstract: In a method of manufacturing a vertical semiconductor device, an insulation layer and a sacrificial layer are alternatively and repeatedly formed on a substrate to define a structure. The structure is etched to form a hole therethrough that exposes the substrate. A first semiconductor pattern is formed in a lower portion of the hole, and a blocking pattern, a charge storage pattern, a tunnel insulation pattern and a first channel pattern are formed on a sidewall of the hole. A second channel pattern is formed on the first channel pattern and the semiconductor pattern, and a second semiconductor pattern is formed on a portion of the second channel pattern on the semiconductor pattern to define an upper channel pattern including the second channel pattern and the second semiconductor pattern. The sacrificial layers are replaced with a plurality of gates, respectively, including a conductive material.

公开(公告)号：US10242997B2

公开(公告)日：2019-03-26

申请号：US15223255

申请日：2016-07-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chang-Min Choi ,  Ju-Young Lim ,  Su-Jin Ahn

IPC: H01L27/108 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11565 ,  H01L27/06 ,  H01L27/11578 ,  H01L23/528 ,  H01L27/1157 ,  H01L27/11575

Abstract: A vertical memory device includes a substrate, a plurality of channels extending in a first direction substantially vertical to a top surface of the substrate, a plurality of gate lines surrounding a predetermined number of channels from among the channels, a plurality of common wirings electrically connected to the gate lines, and a plurality of signal wirings electrically connected to the gate lines via the common wirings. The gate lines are arranged and spaced apart from one another along the first direction. Each common wiring is electrically connected to a corresponding gate line at a same level of the corresponding gate line via a corresponding contact.