公开(公告)号：US10748929B2

公开(公告)日：2020-08-18

申请号：US16739417

申请日：2020-01-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changhyun Lee ,  Chanjin Park ,  Byoungkeun Son ,  Sung-Il Chang

IPC: H01L27/11582 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/06 ,  H01L29/792

Abstract: A three-dimensional semiconductor device includes an upper structure on a lower structure, the upper structure including conductive patterns, a semiconductor pattern connected to the lower structure through the upper structure, and an insulating spacer between the semiconductor pattern and the upper structure, a bottom surface of the insulating spacer being positioned at a vertical level equivalent to or higher than an uppermost surface of the lower structure.

公开(公告)号：US10559590B2

公开(公告)日：2020-02-11

申请号：US16021295

申请日：2018-06-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changhyun Lee ,  Chanjin Park ,  Byoungkeun Son ,  Sung-Il Chang

IPC: H01L27/11578 ,  H01L27/11582 ,  H01L27/11551 ,  H01L27/11556 ,  H01L29/06 ,  H01L29/792

Abstract: A three-dimensional semiconductor device includes an upper structure on a lower structure, the upper structure including conductive patterns, a semiconductor pattern connected to the lower structure through the upper structure, and an insulating spacer between the semiconductor pattern and the upper structure, a bottom surface of the insulating spacer being positioned at a vertical level equivalent to or higher than an uppermost surface of the lower structure.

公开(公告)号：US09240419B2

公开(公告)日：2016-01-19

申请号：US14515997

申请日：2014-10-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Il Chang ,  Changhyun Lee ,  Byoungkeun Son ,  Jin-Soo Lim

IPC: H01L21/00 ,  H01L27/115 ,  H01L29/423 ,  H01L21/822 ,  H01L27/06 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L27/11582 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/31111 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/11556 ,  H01L29/4232 ,  H01L29/42372

Abstract: Three-dimensional semiconductor devices are provided. The three-dimensional semiconductor device includes a substrate, a buffer layer on the substrate. The buffer layer includes a material having an etching selectivity relative to that of the substrate. A multi-layer stack including alternating insulation patterns and conductive patterns is provided on the buffer layer opposite the substrate. One or more active patterns respectively extend through the alternating insulation patterns and conductive patterns of the multi-layer stack and into the buffer layer. Related fabrication methods are also discussed.

Abstract translation: 提供三维半导体器件。 三维半导体器件包括衬底，衬底上的缓冲层。 缓冲层包括具有相对于衬底的蚀刻选择性的材料。 在与衬底相对的缓冲层上提供包括交替绝缘图案和导电图案的多层堆叠。 一个或多个有源图案分别延伸穿过多层堆叠的交替绝缘图案和导电图案并进入缓冲层。 还讨论了相关的制造方法。

公开(公告)号：US10367002B2

公开(公告)日：2019-07-30

申请号：US15288517

申请日：2016-10-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Il Chang ,  Jun-Hee Lim ,  Yong-Seok Kim ,  Tae-Young Kim ,  Jae-Sung Sim ,  Su-Jin Ahn ,  Ji-Yeong Hwang

IPC: H01L27/11582 ,  H01L27/11578 ,  H01L29/66 ,  H01L21/265 ,  H01L27/11556 ,  H01L29/78 ,  H01L27/1157

Abstract: In a method of manufacturing a vertical semiconductor device, an insulation layer and a sacrificial layer are alternatively and repeatedly formed on a substrate to define a structure. The structure is etched to form a hole therethrough that exposes the substrate. A first semiconductor pattern is formed in a lower portion of the hole, and a blocking pattern, a charge storage pattern, a tunnel insulation pattern and a first channel pattern are formed on a sidewall of the hole. A second channel pattern is formed on the first channel pattern and the semiconductor pattern, and a second semiconductor pattern is formed on a portion of the second channel pattern on the semiconductor pattern to define an upper channel pattern including the second channel pattern and the second semiconductor pattern. The sacrificial layers are replaced with a plurality of gates, respectively, including a conductive material.

公开(公告)号：US11107833B2

公开(公告)日：2021-08-31

申请号：US16860113

申请日：2020-04-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changhyun Lee ,  Chanjin Park ,  Byoungkeun Son ,  Sung-Il Chang

IPC: H01L27/11582 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/06 ,  H01L29/792

Abstract: A three-dimensional semiconductor device includes an upper structure on a lower structure, the upper structure including conductive patterns, a semiconductor pattern connected to the lower structure through the upper structure, and an insulating spacer between the semiconductor pattern and the upper structure, a bottom surface of the insulating spacer being positioned at a vertical level equivalent to or higher than an uppermost surface of the lower structure.

公开(公告)号：US09142563B2

公开(公告)日：2015-09-22

申请号：US14599621

申请日：2015-01-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Il Chang ,  Youngwoo Park ,  Jaegoo Lee

IPC: H01L29/792 ,  H01L27/115 ,  H01L21/311

CPC classification number: H01L27/11582 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31111 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/42324 ,  H01L29/4234

Abstract: A 3D semiconductor device includes an electrode structure has electrodes stacked on a substrate, semiconductor patterns penetrating the electrode structure, charge storing patterns interposed between the semiconductor patterns and the electrode structure, and blocking insulating patterns interposed between the charge storing patterns and the electrode structure. Each of the blocking insulating patterns surrounds the semiconductor patterns, and the charge storing patterns are horizontally spaced from each other and configured in such a way as to each be disposed around a respective one of the semiconductor patterns. Also, each of the charge storing patterns includes a plurality of horizontal segments, each interposed between vertically adjacent ones of the electrodes.

公开(公告)号：US20150132906A1

公开(公告)日：2015-05-14

申请号：US14599621

申请日：2015-01-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Il Chang ,  Young Woo Park ,  Jae Goo Lee

IPC: H01L27/115 ,  H01L21/311

CPC classification number: H01L27/11582 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31111 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/42324 ,  H01L29/4234

Abstract: A 3D semiconductor device includes an electrode structure has electrodes stacked on a substrate, semiconductor patterns penetrating the electrode structure, charge storing patterns interposed between the semiconductor patterns and the electrode structure, and blocking insulating patterns interposed between the charge storing patterns and the electrode structure. Each of the blocking insulating patterns surrounds the semiconductor patterns, and the charge storing patterns are horizontally spaced from each other and configured in such a way as to each be disposed around a respective one of the semiconductor patterns. Also, each of the charge storing patterns includes a plurality of horizontal segments, each interposed between vertically adjacent ones of the electrodes.

公开(公告)号：USRE50089E1

公开(公告)日：2024-08-20

申请号：US17732950

申请日：2022-04-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Il Chang ,  Changhyun Lee ,  Byoungkeun Son ,  Jin-Soo Lim

IPC: H01L29/423 ,  H01L21/02 ,  H01L21/311 ,  H01L21/822 ,  H01L27/06 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L29/4232 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/31111 ,  H01L21/8221 ,  H01L27/0688 ,  H01L29/42372 ,  H10B41/27 ,  H10B43/27

Abstract: Three-dimensional semiconductor devices are provided. The three-dimensional semiconductor device includes a substrate, a buffer layer on the substrate. The buffer layer includes a material having an etching selectivity relative to that of the substrate. A multi-layer stack including alternating insulation patterns and conductive patterns is provided on the buffer layer opposite the substrate. One or more active patterns respectively extend through the alternating insulation patterns and conductive patterns of the multi-layer stack and into the buffer layer. Related fabrication methods are also discussed.

公开(公告)号：US20200258908A1

公开(公告)日：2020-08-13

申请号：US16860113

申请日：2020-04-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changhyun Lee ,  Chanjin Park ,  Byoungkeun Son ,  Sung-Il Chang

IPC: H01L27/11582 ,  H01L29/792 ,  H01L29/06 ,  H01L27/11578 ,  H01L27/11556 ,  H01L27/11551

Abstract: A three-dimensional semiconductor device includes an upper structure on a lower structure, the upper structure including conductive patterns, a semiconductor pattern connected to the lower structure through the upper structure, and an insulating spacer between the semiconductor pattern and the upper structure, a bottom surface of the insulating spacer being positioned at a vertical level equivalent to or higher than an uppermost surface of the lower structure.

公开(公告)号：US08796091B2

公开(公告)日：2014-08-05

申请号：US14012588

申请日：2013-08-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Il Chang ,  Youngwoo Park ,  Kwang Soo Seol

IPC: H01L21/336

CPC classification number: H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

Abstract: Provided are three-dimensional semiconductor devices. A device includes an electrode structure including conductive patterns sequentially stacked on a substrate, a semiconductor pattern penetrating the electrode structure and including channel regions adjacent to the conductive patterns and vertical adjacent regions between the channel regions, and a semiconductor connecting layer extending from an outer sidewall of the semiconductor pattern to connect the semiconductor pattern to the substrate.

Abstract translation: 提供三维半导体器件。 一种器件包括：电极结构，包括依次层叠在衬底上的导电图案，穿透电极结构的半导体图案，以及包括与导电图案相邻的沟道区域和沟道区域之间的垂直相邻区域;以及从外侧壁延伸的半导体连接层 的半导体图案以将半导体图案连接到基板。