公开(公告)号：US11517164B2

公开(公告)日：2022-12-06

申请号：US16911857

申请日：2020-06-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woo Jin Na ,  Hakbong Lee ,  Bosang Kim ,  Sin-Ae Kim ,  Yong-Seok Kim ,  Yeonkyu Jeong

IPC: A47L9/14 ,  A47L5/22 ,  A47L9/28 ,  A47L9/10

Abstract: Provided is a cleaning system including: a robot cleaner including a dust collecting device having a dirt outlet and an outlet door configured to open and close the dirt outlet; and a station including a collecting device configured to generate a suction force to suction dirt of the duct collecting device and a lever device provided with a lever configured to be fixable to the outlet door as the outlet door is being opened to allow the collecting device and the dust collecting device to communicate with each other, and a lever driving source configured to generate power for driving the lever.

公开(公告)号：US10861874B2

公开(公告)日：2020-12-08

申请号：US16445433

申请日：2019-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Hwan Lee ,  Yong-Seok Kim ,  Jun-Hee Lim ,  Kohji Kanamori

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L21/311 ,  H01L21/768 ,  H01L21/762

Abstract: A vertical semiconductor device includes conductive pattern structures extending in a first direction, a trench between two adjacent conductive pattern structures in a second direction crossing the first direction, a memory layer disposed on sidewalls of the trench, first insulation layers disposed in the trench and spaced apart from each other in the first direction, channel patterns disposed on the memory layer and in the trench and spaced apart from each other in the first direction, and etch stop layer patterns disposed in the trench. Each conductive pattern structure includes conductive patterns and insulation layers alternately stacked on an upper surface of the substrate. Each etch stop layer pattern is disposed between a corresponding first insulation layer and the blocking dielectric layer. Etch stop layer patterns are spaced apart from each other in the first direction.

公开(公告)号：US09595612B2

公开(公告)日：2017-03-14

申请号：US15006522

申请日：2016-01-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Hwan Kim ,  Hun-Hyeoung Leam ,  Tae-Hyun Kim ,  Seok-Woo Nam ,  Hyun Namkoong ,  Yong-Seok Kim ,  Tea-Kwang Yu

IPC: H01L29/76 ,  H01L29/78 ,  H01L21/28 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/115 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/785 ,  H01L21/28282 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/823481 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/1079 ,  H01L29/42352 ,  H01L29/66818 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/7854 ,  H01L2029/7858

Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.

Abstract translation: 半导体器件包括限定形成在半导体衬底中的有源区的隔离层。 在隔离层上执行第一凹陷处理以暴露活性区域的边缘部分。 执行第一舍入处理以围绕活动区域的边缘部分。 在隔离层上进行第二凹陷处理。 执行第二舍入处理以围绕活动区域的边缘部分。

公开(公告)号：US09184232B2

公开(公告)日：2015-11-10

申请号：US14538046

申请日：2014-11-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Hwan Kim ,  Hun-Hyeoung Leam ,  Tae-Hyun Kim ,  Seok-Woo Nam ,  Hyun Namkoong ,  Yong-Seok Kim ,  Tea-Kwang Yu

IPC: H01L29/06 ,  H01L21/28 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/115 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L21/28282 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/823481 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/1079 ,  H01L29/42352 ,  H01L29/66818 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/7854 ,  H01L2029/7858

Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.

公开(公告)号：US20130320461A1

公开(公告)日：2013-12-05

申请号：US13960434

申请日：2013-08-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUNG-HWAN KIM ,  Hun-Hyeoung Leam ,  Tae-Hyun Kim ,  Seok-Woo Nam ,  Hyun Namkoong ,  Yong-Seok Kim ,  Tea-Kwang Yu

IPC: H01L29/78

CPC classification number: H01L29/785 ,  H01L21/28282 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/823481 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/1079 ,  H01L29/42352 ,  H01L29/66818 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/7854 ,  H01L2029/7858

Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.

公开(公告)号：US11152390B2

公开(公告)日：2021-10-19

申请号：US16903070

申请日：2020-06-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Il Chang ,  Jun-Hee Lim ,  Yong-Seok Kim ,  Tae-Young Kim ,  Jae-Sung Sim ,  Su-Jin Ahn ,  Ji-Yeong Hwang

IPC: H01L27/11582 ,  H01L27/11578 ,  H01L29/66 ,  H01L29/78 ,  H01L27/1157 ,  H01L21/265 ,  H01L27/11556

Abstract: In a method of manufacturing a vertical semiconductor device, an insulation layer and a sacrificial layer are alternatively and repeatedly formed on a substrate to define a structure. The structure is etched to form a hole therethrough that exposes the substrate. A first semiconductor pattern is formed in a lower portion of the hole, and a blocking pattern, a charge storage pattern, a tunnel insulation pattern and a first channel pattern are formed on a sidewall of the hole. A second channel pattern is formed on the first channel pattern and the semiconductor pattern, and a second semiconductor pattern is formed on a portion of the second channel pattern on the semiconductor pattern to define an upper channel pattern including the second channel pattern and the second semiconductor pattern. The sacrificial layers are replaced with a plurality of gates, respectively, including a conductive material.

公开(公告)号：US10763167B2

公开(公告)日：2020-09-01

申请号：US16243338

申请日：2019-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Hwan Lee ,  Chang-Seok Kang ,  Yong-Seok Kim ,  Jun-Hee Lim ,  Kohji Kanamori

IPC: H01L21/768 ,  H01L23/522 ,  H01L27/115 ,  H01L21/3213 ,  H01L21/311

Abstract: A vertical semiconductor device includes a conductive pattern structure in which insulation patterns and conductive patterns alternately and repeatedly stacked on the substrate. The conductive pattern structure includes an edge portion having a stair-stepped shape. Each of the conductive patterns includes a pad region corresponding to an upper surface of a stair in the edge portion. A pad conductive pattern is disposed to contact a portion of an upper surface of the pad region. A mask pattern is disposed on an upper surface of the pad conductive pattern. A contact plug penetrates the mask pattern to contact the pad conductive pattern.

公开(公告)号：US10700092B2

公开(公告)日：2020-06-30

申请号：US16441163

申请日：2019-06-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Il Chang ,  Jun-Hee Lim ,  Yong-Seok Kim ,  Tae-Young Kim ,  Jae-Sung Sim ,  Su-Jin Ahn ,  Ji-Yeong Hwang

IPC: H01L27/11582 ,  H01L27/11578 ,  H01L29/66 ,  H01L29/78 ,  H01L27/1157 ,  H01L21/265 ,  H01L27/11556

Abstract: In a method of manufacturing a vertical semiconductor device, an insulation layer and a sacrificial layer are alternatively and repeatedly formed on a substrate to define a structure. The structure is etched to form a hole therethrough that exposes the substrate. A first semiconductor pattern is formed in a lower portion of the hole, and a blocking pattern, a charge storage pattern, a tunnel insulation pattern and a first channel pattern are formed on a sidewall of the hole. A second channel pattern is formed on the first channel pattern and the semiconductor pattern, and a second semiconductor pattern is formed on a portion of the second channel pattern on the semiconductor pattern to define an upper channel pattern including the second channel pattern and the second semiconductor pattern. The sacrificial layers are replaced with a plurality of gates, respectively, including a conductive material.

公开(公告)号：US10213082B2

公开(公告)日：2019-02-26

申请号：US15670278

申请日：2017-08-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Sik Yoon ,  Kyong Su Kim ,  Shin Kim ,  Yong-Seok Kim ,  Kyung Shik Roh ,  Hyun Soo Jung

IPC: A47L11/40 ,  A47L9/28 ,  G01S15/93 ,  G01S17/88

Abstract: A robot cleaner includes a housing a sensor assembly disposed in the housing, wherein the sensor assembly comprises a light source configured to emit light toward an area in front of the housing; a camera unit comprising a lens; a reflector configured to reflect light incident on a front of the housing toward a front region of the lens; and a guide member hollow inside configured to guide light incident on a top of the housing toward a rear region of the lens. The robot cleaner estimates a current position of the robot cleaner more accurately by correcting the current position of the robot cleaner estimated by using odometry information based on images acquired by the camera unit.

公开(公告)号：US09847422B2

公开(公告)日：2017-12-19

申请号：US15290269

申请日：2016-10-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Hwan Kim ,  Hun-Hyeoung Leam ,  Tae-Hyun Kim ,  Seok-Woo Nam ,  Hyun Namkoong ,  Yong-Seok Kim ,  Tea-Kwang Yu

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L21/308

CPC classification number: H01L29/785 ,  H01L21/28282 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/823481 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/1079 ,  H01L29/42352 ,  H01L29/66818 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/7854 ,  H01L2029/7858

Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.