-
公开(公告)号：US11601611B2
公开(公告)日：2023-03-07
申请号：US17523100
申请日：2021-11-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyuk Oh , Sungyong Kim , Beomsu Yun
Abstract: An image sensor is provided. The image sensor includes a counting code generator configured to generate a counting code, a pixel array including at least one pixel, a correlated double sampling (CDS) circuit configured to compare a magnitude of a pixel signal output from the at least one pixel with a magnitude of a ramp signal and to output a corresponding comparison signal, a pulse generator configured to generate a pulse signal synchronized with a first clock signal based on the comparison signal, and a counter circuit configured to latch a value of the counting code to correspond to a transition of a level of the comparison signal based on the pulse signal.
-
公开(公告)号：US11445142B2
公开(公告)日：2022-09-13
申请号：US17465586
申请日：2021-09-02
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sungyong Kim
Abstract: A digital correlated double sampling circuit includes a first latch circuit, a second latch circuit, a decision circuit, a delay control circuit and a calculating circuit. The first latch circuit stores first reset component data. The second latch circuit stores second reset component data and stores image component data based on a selected comparison signal during an image interval. The decision circuit outputs a decision signal by determining identity of the first reset component data and the second reset component data during the reset interval. The delay control circuit outputs the reset comparison signal and outputs one of the first image comparison signal and the second comparison signal as the selected comparison signal. The calculating circuit generates effective image data by subtracting the second reset component data from the image component data and sequentially outputs the effective image data.
-
Patent Agency Ranking
公开(公告)号：US20230261499A1
公开(公告)日：2023-08-17
申请号：US18138496
申请日：2023-04-24
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yeongil KIM , Seungbeom Kang , Sungyong Kim , Sanghyun Ryu , Hyunjun Oh
IPC: H02J7/00
CPC classification number: H02J7/00718 , H02J7/00716
Abstract: An electronic includes: a battery; a power supply circuit electrically connected to the battery; and a processor configured to receive power through the power supply circuit, wherein the power supply circuit may be further configured to, based on a ship mode command received from the processor at a first time, switch an operation mode of the electronic device to a ship mode of the electronic device by shutting off power supplied to the processor by the battery at a second time that is delayed from the first time by a preset time.
-
公开(公告)号：US10419003B1
公开(公告)日：2019-09-17
申请号：US16209195
申请日：2018-12-04
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sungyong Kim
Abstract: Disclosed is a gray code generator. The gray code generator includes a counter that counts first to fourth digital bits in response to a clock signal, and a converter that converts the first to fourth digital bits to first to fourth gray bits. The counter includes a replica flip-flop that outputs the clock signal as the first digital bit, a first flip-flop that inverts the second digital bit in response to the clock signal to output the second digital bit, a second flip-flop that outputs a high level in response to the clock signal when a second inverted digital bit is different from a third inverted digital bit, and a third flip-flop that outputs the high level in response to the clock signal when a result of performing a NOR operation on the second and third inverted digital bits is different from a fourth inverted digital bit.
-
公开(公告)号：US11303835B2
公开(公告)日：2022-04-12
申请号：US16996264
申请日：2020-08-18
Applicant: Samsung Electronics Co., Ltd.
Inventor： Myunglae Chu , Sungyong Kim , Seoksan Kim , Minwoong Seo , Jaekyu Lee , Jongyeon Lee , Junan Lee
IPC: H04N5/3745 , H04N5/378
Abstract: Provided are a pixel array and an image sensor. The pixel array includes a plurality of pixels, which are arranged in a matrix form and which convert an optical signal into an electrical signal. The pixel array includes a first pixel arranged in a first row of the pixel array and a second pixel arranged in a second row of the pixel array, wherein each of the first pixel and the second pixel includes a first memory storing a digital reset value according to internal noise, the first memory of the first pixel stores m-bit data (where m is a natural number equal to or greater than 2), and the first memory of the second pixel stores n-bit data (where n is a natural number less than m).
-
公开(公告)号：US11245864B2
公开(公告)日：2022-02-08
申请号：US16907776
申请日：2020-06-22
Applicant: Samsung Electronics Co., Ltd.
Inventor： Junan Lee , Sungyong Kim
IPC: H04N5/378 , H04N5/3745 , H03M1/50
Abstract: A comparator includes a comparison circuit and a positive feedback circuit. The comparison circuit generates a comparison signal by comparing an input signal and a reference signal. The positive feedback circuit generates an output signal based on the comparison signal, such that the output signal transitions more rapidly than the comparison signal. The positive feedback circuit includes a first circuit configured to electrically connect a first power supply voltage to a conversion node in response to a transition of the comparison signal and electrically disconnect the first power supply voltage from the conversion node in response to a transition of the output signal, a second circuit configured to electrically connect a second power supply voltage to the conversion node in response to the transition of the output signal, and an output circuit configured to generate the output signal based on a voltage of the conversion node.
-
公开(公告)号：US20190296745A1
公开(公告)日：2019-09-26
申请号：US16209195
申请日：2018-12-04
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sungyong Kim
Abstract: Disclosed is a gray code generator. The gray code generator includes a counter that counts first to fourth digital bits in response to a clock signal, and a converter that converts the first to fourth digital bits to first to fourth gray bits. The counter includes a replica flip-flop that outputs the clock signal as the first digital bit, a first flip-flop that inverts the second digital bit in response to the clock signal to output the second digital bit, a second flip-flop that outputs a high level in response to the clock signal when a second inverted digital bit is different from a third inverted digital bit, and a third flip-flop that outputs the high level in response to the clock signal when a result of performing a NOR operation on the second and third inverted digital bits is different from a fourth inverted digital bit.
-
-
-
-
-
-
Search Results
7
records
(took 0.014 seconds)
