公开(公告)号：US20180197608A1

公开(公告)日：2018-07-12

申请号：US15834142

申请日：2017-12-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Ho SONG ,  Tae-Hong KWON ,  Yo-Han LEE

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/12

CPC classification number: G11C16/08 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/3495 ,  H01L27/11556 ,  H01L27/11582

Abstract: A high voltage switch circuit of a nonvolatile memory device includes a high voltage transistor, logic, and a high voltage switch. The high voltage transistor is turned-on based on a program turn-on voltage and transfers a program voltage to a first memory block. The logic generates path selection signals based on an enable signal and switching control signals based on one of an operating parameter of the nonvolatile memory device or an access address for at least a portion of the first memory block. The enable signal is activated during a program operation on the first memory block. The high voltage switch delivers the program turn-on voltage to a gate of the high voltage transistor via one of a plurality of delivery paths based on the path selection signals. As a result, influence of a negative bias temperature instability (NBTI) generated by the program turn-on voltage is dispersed.

公开(公告)号：US20240029798A1

公开(公告)日：2024-01-25

申请号：US18176347

申请日：2023-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-Hong KWON ,  Kiwhan Song ,  Gyosoo Choo

IPC: G11C16/26 ,  G11C16/20 ,  G11C16/04

CPC classification number: G11C16/26 ,  G11C16/20 ,  G11C16/0433

Abstract: Various example embodiments provide a flash memory device, comprising a cell string having a plurality of memory cells; a page buffer connected to the cell string and a bit line and configured to sense data stored in a selected memory cell from among the plurality of memory cells by precharging a sensing node connected to the bit line; and a voltage regulator providing a source voltage to the page buffer. The page buffer comprises a latch including first and second inverters coupled between a latch node and an inverted latch node; and a pull-down NMOS transistor for tripping the sensing result of the selected memory cell to the latch node. The voltage regulator adjusts a trip voltage by providing the source voltage to the pull-down NMOS transistor. The flash memory device according to the embodiment of the present invention may reduce a trip voltage variation range by using only the pull-down NMOS transistor characteristics. Also, according to the present invention, an OFF cell margin and an ON cell margin may be sufficiently secured by adjusting the level of the trip voltage Vtrip using the source voltage Vs.

公开(公告)号：US20250095745A1

公开(公告)日：2025-03-20

申请号：US18677536

申请日：2024-05-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae-Hong KWON ,  Gyosoo CHOO ,  Myung Uk PARK ,  Donggeun LEE

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/16

Abstract: A flash memory includes a memory block connected to word lines, an address decoder that selects one or more of the word lines, a first pass transistor connected to the address decoder, a second pass transistor connected in series with the first pass transistor and connected to one word line among the word lines, a first driver circuit that controls a gate voltage of the first pass transistor based on a first enable signal, and a second driver circuit that controls a gate voltage of the second pass transistor based on a second enable signal. Based on the memory block being an unselected memory block during an erase operation, the first driver circuit controls the first pass transistor to be in a floating state, the second driver circuit controls a power voltage to be provided to a gate of the second pass transistor.

公开(公告)号：US20210193679A1

公开(公告)日：2021-06-24

申请号：US16993570

申请日：2020-08-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae-Hong KWON ,  Chan Ho KIM ,  Kyung Hwa YUN ,  Dae Seok BYEON ,  Chi Weon YOON

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  G11C5/14 ,  G11C16/08 ,  G11C16/24 ,  G11C16/32

Abstract: Provided is a semiconductor memory device. In order to permit dense integration of a high number of stacked word lines in the semiconductor memory device, a charge pump is included in the semiconductor Mary device. The charge pump makes use of a capacitor. The capacitor is implemented with respect to the dense integration. Some components are placed under the stacked word lines, and some are not under the stacked word lines. The capacity of the capacitor not under the stacked word lines is provided in part by a parallel structure.