公开(公告)号：US09667241B2

公开(公告)日：2017-05-30

申请号：US14863935

申请日：2015-09-24

Applicant: Samsung Electronics Co., Ltd. ,  Postech Academy-Industry Foundation

Inventor： Jaesup Lee ,  Tae-Young Chung ,  Bum-Man Kim ,  Dae-Chul Jeong

IPC: H03K5/131 ,  H03K17/284 ,  H03K17/292 ,  H03K5/00

CPC classification number: H03K17/292 ,  H03K5/131 ,  H03K17/284 ,  H03K2005/00019 ,  H03K2005/00195

Abstract: A leakage current-based delay circuit is provided, wherein the delay circuit may include a first transistor circuit and a second transistor circuit, each transistor circuit may include a p-type transistor, an n-type transistor, an n-node between a drain node of the p-type transistor and a gate node of the n-type transistor, and a p-node between a gate node of the p-type transistor and a drain node of the n-type transistor. The p-node of the second transistor circuit may be charged based on a power source voltage through the first transistor circuit during a first time interval of an input signal, and the n-node of the second transistor circuit may be discharged based on a ground voltage through the first transistor circuit during the first time interval.

公开(公告)号：US09099325B2

公开(公告)日：2015-08-04

申请号：US14109517

申请日：2013-12-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Sung Kim ,  Tae-Young Chung ,  Soo-Ho Shin

IPC: H01L29/76 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088

CPC classification number: H01L21/28123 ,  H01L21/76224 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/10826 ,  H01L27/10879 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/4238 ,  H01L29/66795 ,  H01L29/7802 ,  H01L29/7827 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7853

Abstract: A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The device includes gate electrodes formed on element isolation layers that are disposed between active regions and have top surfaces that are higher than the top surfaces of the active regions. Since the gate electrodes are formed on the element isolation layers, leakage current in a semiconductor substrate is prevented. In addition, the gate electrodes are formed using a striped shape mask pattern, thereby obtaining a sufficient overlap margin compared to a contact shape or bar shape pattern.