公开(公告)号：US11785767B2

公开(公告)日：2023-10-10

申请号：US17159727

申请日：2021-01-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngwoo Kim ,  Dawoon Jeong ,  Tak Lee ,  Jungmin Lee

IPC: H10B41/27 ,  H10B41/10 ,  H10B43/10 ,  H10B43/27

CPC classification number: H10B41/27 ,  H10B41/10 ,  H10B43/10 ,  H10B43/27

Abstract: A semiconductor device includes a substrate having a first region and a second region, insulating patterns in the substrate in the second region that define active patterns of the substrate, gate electrodes spaced apart from each other and stacked on an upper surface of the substrate and extending in a first direction, first separation regions extending in the first direction and in contact with the active patterns, second separation regions extending between the first separation regions in the first direction, and channel structures penetrating through the gate electrodes in the first region. At least one of the second separation regions is in contact with the substrate below the insulating patterns.

公开(公告)号：US20190035805A1

公开(公告)日：2019-01-31

申请号：US15941917

申请日：2018-03-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byoung-Il Lee ,  Ji-Mo Gu ,  Hyun-Mog Park ,  Tak Lee ,  Jun-Ho Cha ,  Sang-Jun Hong

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L29/10 ,  H01L29/423

Abstract: A vertical memory device includes gate electrodes spaced apart from each other in a first direction. Each of the gate electrodes extends in a second direction. Insulation patterns extend in the second direction between adjacent gate electrodes. A channel structure extends in the first direction. The channel structure extends through at least a portion of the gate electrode structure and at least a portion of the insulation pattern structure. The gate electrode structure includes at least one first gate electrode and a plurality of second gate electrodes sequentially stacked in the first direction on the substrate. Lower and upper surfaces of a first insulation pattern are bent away from the upper surface of the substrate along the first direction. A sidewall connecting the lower and upper surfaces of the first insulation pattern is slanted with respect to the upper surface of the substrate.

公开(公告)号：US11011536B2

公开(公告)日：2021-05-18

申请号：US15941917

申请日：2018-03-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byoung-Il Lee ,  Ji-Mo Gu ,  Hyun-Mog Park ,  Tak Lee ,  Jun-Ho Cha ,  Sang-Jun Hong

IPC: H01L27/11582 ,  H01L29/423 ,  H01L29/10 ,  H01L27/1157

Abstract: A vertical memory device includes gate electrodes spaced apart from each other in a first direction. Each of the gate electrodes extends in a second direction. Insulation patterns extend in the second direction between adjacent gate electrodes. A channel structure extends in the first direction. The channel structure extends through at least a portion of the gate electrode structure and at least a portion of the insulation pattern structure. The gate electrode structure includes at least one first gate electrode and a plurality of second gate electrodes sequentially stacked in the first direction on the substrate. Lower and upper surfaces of a first insulation pattern are bent away from the upper surface of the substrate along the first direction. A sidewall connecting the lower and upper surfaces of the first insulation pattern is slanted with respect to the upper surface of the substrate.

公开(公告)号：US11004866B2

公开(公告)日：2021-05-11

申请号：US16791218

申请日：2020-02-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tak Lee ,  Su Bin Kang ,  Ji Mo Gu ,  Yu Jin Seo ,  Byoung il Lee ,  Jun Ho Cha

IPC: H01L27/11578 ,  H01L27/11582 ,  H01L27/11568 ,  H01L29/10 ,  H01L29/423 ,  H01L21/285 ,  H01L27/11565 ,  H01L27/11575 ,  H01L21/02 ,  H01L21/311 ,  H01L21/28

Abstract: A vertical-type memory device includes a substrate having a cell array region and a connection region disposed adjacent to the cell array region, a plurality of gate electrode layers stacked on the cell array region and the connection region, a plurality of channel structures disposed in the cell array region, a plurality of dummy channel structures disposed in the connection region, and a plurality of slits disposed in the plurality of gate electrode layers in the cell array region. The plurality of gate electrode layers forms a stepped structure in the connection region, the plurality of channel structures penetrates the plurality of gate electrode layers, and the plurality of dummy channel structures penetrates at least one of the plurality of gate electrode layers.

公开(公告)号：US10515974B2

公开(公告)日：2019-12-24

申请号：US15925365

申请日：2018-03-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoung Il Lee ,  Ji Mo Gu ,  Tak Lee ,  Jun Ho Cha

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11529 ,  H01L27/11548 ,  H01L27/11575 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11565

Abstract: A semiconductor device includes a substrate having first and second regions, a gate electrode stack having a plurality of gate electrodes vertically stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the substrate in the first region, and extending to have different lengths in a second direction parallel to the upper surface of the substrate from the first region to the second region, first and second isolation regions extending in the second direction perpendicular to the first direction, while penetrating through the gate electrode stack on the substrate, in the first and second regions, string isolation regions disposed between the first and second isolation regions in the first region, and extending in the second direction while penetrating through a portion of the gate electrode stack, and a plurality of auxiliary isolation regions disposed linearly with the string isolation regions in at least one of the first and second regions, and spaced apart from each other in the second direction.

公开(公告)号：US20190244969A1

公开(公告)日：2019-08-08

申请号：US16108834

申请日：2018-08-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tak Lee ,  Su Bin Kang ,  Ji Mo Gu ,  Yu Jin Seo ,  Byoung Il Lee ,  Jun Ho Cha

IPC: H01L27/11582 ,  H01L27/11568 ,  H01L29/10 ,  H01L29/423 ,  H01L27/11565 ,  H01L21/285

Abstract: A vertical-type memory device includes a substrate having a cell array region and a connection region disposed adjacent to the cell array region, a plurality of gate electrode layers stacked on the cell array region and the connection region, a plurality of channel structures disposed in the cell array region, a plurality of dummy channel structures disposed in the connection region, and a plurality of slits disposed in the plurality of gate electrode layers in the cell array region. The plurality of gate electrode layers forms a stepped structure in the connection region, the plurality of channel structures penetrates the plurality of gate electrode layers, and the plurality of dummy channel structures penetrates at least one of the plurality of gate electrode layers.

公开(公告)号：US20210391346A1

公开(公告)日：2021-12-16

申请号：US17159727

申请日：2021-01-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngwoo Kim ,  Dawoon Jeong ,  Tak Lee ,  Jungmin Lee

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11565

Abstract: A semiconductor device includes a substrate having a first region and a second region, insulating patterns in the substrate in the second region that define active patterns of the substrate, gate electrodes spaced apart from each other and stacked on an upper surface of the substrate and extending in a first direction, first separation regions extending in the first direction and in contact with the active patterns, second separation regions extending between the first separation regions in the first direction, and channel structures penetrating through the gate electrodes in the first region. At least one of the second separation regions is in contact with the substrate below the insulating patterns.

公开(公告)号：US10998327B2

公开(公告)日：2021-05-04

申请号：US16227822

申请日：2018-12-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Su Bin Kang ,  Byoung Il Lee ,  Ji Mo Gu ,  Yu Jin Seo ,  Tak Lee

IPC: H01L27/11565 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/1157 ,  H01L27/11556

Abstract: A semiconductor device includes a stacked structure disposed on a substrate. The stacked structure includes a plurality of gate electrodes. The semiconductor device further includes a first structure disposed on the substrate and passing through the stacked structure, and a second structure disposed on the substrate. The second structure is disposed outside of the stacked structure, faces the first structure, and is spaced apart from the first structure. The first structure includes a plurality of separation lines passing through at least a portion of the plurality of gate electrodes and extending outside of the stacked structure, and the second structure is formed of the same material as the first structure.

公开(公告)号：US10672781B2

公开(公告)日：2020-06-02

申请号：US16724444

申请日：2019-12-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoung Il Lee ,  Ji Mo Gu ,  Tak Lee ,  Jun Ho Cha

IPC: H01L27/11556 ,  H01L27/11573 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11548 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11575

Abstract: A semiconductor device includes a substrate having first and second regions, a gate electrode stack having a plurality of gate electrodes vertically stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the substrate in the first region, and extending to have different lengths in a second direction parallel to the upper surface of the substrate from the first region to the second region, first and second isolation regions extending in the second direction perpendicular to the first direction, while penetrating through the gate electrode stack on the substrate, in the first and second regions, string isolation regions disposed between the first and second isolation regions in the first region, and extending in the second direction while penetrating through a portion of the gate electrode stack, and a plurality of auxiliary isolation regions disposed linearly with the string isolation regions in at least one of the first and second regions, and spaced apart from each other in the second direction.

公开(公告)号：US12114497B2

公开(公告)日：2024-10-08

申请号：US18464668

申请日：2023-09-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngwoo Kim ,  Dawoon Jeong ,  Tak Lee ,  Jungmin Lee

IPC: H10B41/27 ,  H10B41/10 ,  H10B43/10 ,  H10B43/27

CPC classification number: H10B41/27 ,  H10B41/10 ,  H10B43/10 ,  H10B43/27

Abstract: A semiconductor device includes a substrate having a first region and a second region, insulating patterns in the substrate in the second region that define active patterns of the substrate, gate electrodes spaced apart from each other and stacked on an upper surface of the substrate and extending in a first direction, first separation regions extending in the first direction and in contact with the active patterns, second separation regions extending between the first separation regions in the first direction, and channel structures penetrating through the gate electrodes in the first region. At least one of the second separation regions is in contact with the substrate below the insulating patterns.