公开(公告)号：US20210242229A1

公开(公告)日：2021-08-05

申请号：US17218267

申请日：2021-03-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： BYOUNG IL LEE ,  Yu Jin Seo ,  Jun Eon Jin

IPC: H01L27/11565 ,  H01L27/11524 ,  H01L27/11556 ,  H01L23/522 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/528 ,  H01L27/11519

Abstract: A three-dimensional semiconductor device includes first and second extended regions disposed on a substrate spaced apart from each other, a memory block disposed on the substrate between the first and second extended regions, and first and second main separation structures disposed on the substrate spaced apart from each other. The first extended region, the memory block and the second extended region are disposed between the first and second main separation structures. The memory block includes data storage regions and word lines. The word lines extend from the memory block and pass through the first and second extended regions. A distance between the first and second main separation structures located on both sides of the first extended region is greater than a distance between the first and second main separation structures located on both sides of the memory block.

公开(公告)号：US11812609B2

公开(公告)日：2023-11-07

申请号：US17218267

申请日：2021-03-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byoung Il Lee ,  Yu Jin Seo ,  Jun Eon Jin

IPC: H10B43/10 ,  H01L23/522 ,  H10B41/10 ,  H01L23/528 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B43/10 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

Abstract: A three-dimensional semiconductor device includes first and second extended regions disposed on a substrate spaced apart from each other, a memory block disposed on the substrate between the first and second extended regions, and first and second main separation structures disposed on the substrate spaced apart from each other. The first extended region, the memory block and the second extended region are disposed between the first and second main separation structures. The memory block includes data storage regions and word lines. The word lines extend from the memory block and pass through the first and second extended regions. A distance between the first and second main separation structures located on both sides of the first extended region is greater than a distance between the first and second main separation structures located on both sides of the memory block.

公开(公告)号：US11004866B2

公开(公告)日：2021-05-11

申请号：US16791218

申请日：2020-02-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tak Lee ,  Su Bin Kang ,  Ji Mo Gu ,  Yu Jin Seo ,  Byoung il Lee ,  Jun Ho Cha

IPC: H01L27/11578 ,  H01L27/11582 ,  H01L27/11568 ,  H01L29/10 ,  H01L29/423 ,  H01L21/285 ,  H01L27/11565 ,  H01L27/11575 ,  H01L21/02 ,  H01L21/311 ,  H01L21/28

Abstract: A vertical-type memory device includes a substrate having a cell array region and a connection region disposed adjacent to the cell array region, a plurality of gate electrode layers stacked on the cell array region and the connection region, a plurality of channel structures disposed in the cell array region, a plurality of dummy channel structures disposed in the connection region, and a plurality of slits disposed in the plurality of gate electrode layers in the cell array region. The plurality of gate electrode layers forms a stepped structure in the connection region, the plurality of channel structures penetrates the plurality of gate electrode layers, and the plurality of dummy channel structures penetrates at least one of the plurality of gate electrode layers.

公开(公告)号：US20190244969A1

公开(公告)日：2019-08-08

申请号：US16108834

申请日：2018-08-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tak Lee ,  Su Bin Kang ,  Ji Mo Gu ,  Yu Jin Seo ,  Byoung Il Lee ,  Jun Ho Cha

IPC: H01L27/11582 ,  H01L27/11568 ,  H01L29/10 ,  H01L29/423 ,  H01L27/11565 ,  H01L21/285

Abstract: A vertical-type memory device includes a substrate having a cell array region and a connection region disposed adjacent to the cell array region, a plurality of gate electrode layers stacked on the cell array region and the connection region, a plurality of channel structures disposed in the cell array region, a plurality of dummy channel structures disposed in the connection region, and a plurality of slits disposed in the plurality of gate electrode layers in the cell array region. The plurality of gate electrode layers forms a stepped structure in the connection region, the plurality of channel structures penetrates the plurality of gate electrode layers, and the plurality of dummy channel structures penetrates at least one of the plurality of gate electrode layers.

公开(公告)号：US10998327B2

公开(公告)日：2021-05-04

申请号：US16227822

申请日：2018-12-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Su Bin Kang ,  Byoung Il Lee ,  Ji Mo Gu ,  Yu Jin Seo ,  Tak Lee

IPC: H01L27/11565 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/1157 ,  H01L27/11556

Abstract: A semiconductor device includes a stacked structure disposed on a substrate. The stacked structure includes a plurality of gate electrodes. The semiconductor device further includes a first structure disposed on the substrate and passing through the stacked structure, and a second structure disposed on the substrate. The second structure is disposed outside of the stacked structure, faces the first structure, and is spaced apart from the first structure. The first structure includes a plurality of separation lines passing through at least a portion of the plurality of gate electrodes and extending outside of the stacked structure, and the second structure is formed of the same material as the first structure.

公开(公告)号：US10978465B2

公开(公告)日：2021-04-13

申请号：US16227985

申请日：2018-12-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byoung Il Lee ,  Yu Jin Seo ,  Jun Eon Jin

IPC: H01L27/11565 ,  H01L27/11524 ,  H01L27/11556 ,  H01L23/522 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/528 ,  H01L27/11519

Abstract: A three-dimensional semiconductor device includes first and second extended regions disposed on a substrate spaced apart from each other, a memory block disposed on the substrate between the first and second extended regions, and first and second main separation structures disposed on the substrate spaced apart from each other. The first extended region, the memory block and the second extended region are disposed between the first and second main separation structures. The memory block includes data storage regions and word lines. The word lines extend from the memory block and pass through the first and second extended regions. A distance between the first and second main separation structures located on both sides of the first extended region is greater than a distance between the first and second main separation structures located on both sides of the memory block.

公开(公告)号：US10566346B2

公开(公告)日：2020-02-18

申请号：US16108834

申请日：2018-08-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tak Lee ,  Su Bin Kang ,  Ji Mo Gu ,  Yu Jin Seo ,  Byoung Il Lee ,  Jun Ho Cha

IPC: H01L27/11578 ,  H01L27/11582 ,  H01L27/11568 ,  H01L29/10 ,  H01L29/423 ,  H01L21/285 ,  H01L27/11565 ,  H01L21/02 ,  H01L21/311 ,  H01L21/28

Abstract: A vertical-type memory device includes a substrate having a cell array region and a connection region disposed adjacent to the cell array region, a plurality of gate electrode layers stacked on the cell array region and the connection region, a plurality of channel structures disposed in the cell array region, a plurality of dummy channel structures disposed in the connection region, and a plurality of slits disposed in the plurality of gate electrode layers in the cell array region. The plurality of gate electrode layers forms a stepped structure in the connection region, the plurality of channel structures penetrates the plurality of gate electrode layers, and the plurality of dummy channel structures penetrates at least one of the plurality of gate electrode layers.

公开(公告)号：US20190355736A1

公开(公告)日：2019-11-21

申请号：US16227822

申请日：2018-12-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SU BIN KANG ,  Byoung Il Lee ,  Ji Mo Gu ,  Yu Jin Seo ,  Tak Lee

IPC: H01L27/11565 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/1157 ,  H01L27/11582

Abstract: A semiconductor device includes a stacked structure disposed on a substrate. The stacked structure includes a plurality of gate electrodes. The semiconductor device further includes a first structure disposed on the substrate and passing through the stacked structure, and a second structure disposed on the substrate. The second structure is disposed outside of the stacked structure, faces the first structure, and is spaced apart from the first structure. The first structure includes a plurality of separation lines passing through at least a portion of the plurality of gate electrodes and extending outside of the stacked structure, and the second structure is formed of the same material as the first structure.