公开(公告)号：US20140146624A1

公开(公告)日：2014-05-29

申请号：US14087167

申请日：2013-11-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Pil SON ,  Uk-Song KANG ,  Chul-Woo PARK ,  Young-Soo SOHN

IPC: G11C29/00

CPC classification number: G11C29/4401 ,  G06F11/1048 ,  G11C5/04 ,  G11C29/808 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: In one example embodiment, a memory module includes a plurality of memory devices and a buffer chip configured to manage the plurality of memory device. The buffer chip includes a memory management unit having an error correction unit configured to perform error correction operation on each of the plurality of memory devices. Each of the plurality of memory devices includes at least one spare column that is accessible by the memory management unit, and the memory management unit is configured to correct errors of the plurality of memory devices by selectively using the at least one spare column based on an error correction capability of the error correction unit.

Abstract translation: 在一个示例实施例中，存储器模块包括多个存储器件和被配置为管理多个存储器件的缓冲器芯片。 缓冲器芯片包括具有错误校正单元的存储器管理单元，该单元被配置为对多个存储器件中的每一个进行纠错操作。 多个存储器设备中的每一个包括至少一个可由存储器管理单元访问的备用列，并且存储器管理单元被配置为通过有选择地使用至少一个备用列来校正多个存储器件的错误， 纠错单元的纠错能力。

公开(公告)号：US20150309743A1

公开(公告)日：2015-10-29

申请号：US14588496

申请日：2015-01-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Soo SOHN ,  Uk-Song KANG ,  KWANG-IL PARK ,  Chul-Woo PARK ,  Hak-Soo YU ,  Jae-Youn YOUN

IPC: G06F3/06

CPC classification number: G11C11/4087 ,  G11C5/025 ,  G11C7/02 ,  G11C11/4085

Abstract: A semiconductor memory device includes a control logic and a memory cell array in which a plurality of memory cells are arranged. The memory cell array includes a plurality of bank arrays, and each of the plurality of bank arrays includes a plurality of sub-arrays. The control logic controls an access to the memory cell array based on a command and an address signal. The control logic dynamically sets a keep-away zone that includes a plurality of memory cell rows which are deactivated based on a first word-line when the first word-line is enabled. The first word-line is coupled to a first memory cell row of a first sub-array of the plurality of sub-arrays. Therefore, increased timing parameters may be compensated, and parallelism may be increased.

Abstract translation: 半导体存储器件包括控制逻辑和其中布置有多个存储器单元的存储单元阵列。 存储单元阵列包括多个存储体阵列，并且多个存储体阵列中的每一个包括多个子阵列。 控制逻辑基于命令和地址信号控制对存储器单元阵列的访问。 控制逻辑动态地设置包括在第一字线被启用时基于第一字线被去激活的多个存储器单元行的保留区。 第一字线耦合到多个子阵列中的第一子阵列的第一存储单元行。 因此，可以补偿增加的定时参数，并且可以增加并行性。

公开(公告)号：US20140140153A1

公开(公告)日：2014-05-22

申请号：US13804690

申请日：2013-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-Pil SON ,  Jae-Sung KIM ,  Uk-Song KANG ,  Young-Soo SOHN

IPC: G11C29/04

CPC classification number: G11C29/04 ,  G11C29/806 ,  G11C29/808 ,  G11C2029/4402

Abstract: A repair control circuit of controlling a repair operation of a semiconductor memory device includes a row matching block and a column matching block. The row matching block stores fail group information indicating one or more fail row groups among a plurality of row groups. The row groups are determined by grouping a plurality of row addresses corresponding to a plurality of wordlines. The row matching block generates a group match signal based on input row address and the fail group information, such that the group match signal indicates the fail row group including the input row address. The column matching block stores fail column addresses of the fail memory cells, and generates a repair control signal based on input column address, the group match signal and the fail column addresses, such that the repair control signal indicates whether the repair operation is executed or not.

Abstract translation: 控制半导体存储器件的修复操作的修复控制电路包括行匹配块和列匹配块。 行匹配块存储指示多个行组中的一个或多个故障行组的故障组信息。 通过对与多个字线对应的多个行地址进行分组来确定行组。 行匹配块基于输入行地址和故障组信息生成组匹配信号，使得组匹配信号指示包括输入行地址的故障行组。 列匹配块存储故障存储器单元的故障列地址，并且基于输入列地址，组匹配信号和故障列地址生成修复控制信号，使得修复控制信号指示是否执行修复操作或 不。

公开(公告)号：US20140247677A1

公开(公告)日：2014-09-04

申请号：US14081493

申请日：2013-11-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Soo SOHN ,  Chul-Woo PARK ,  Uk-Song KANG ,  Jong-Pil SON

IPC: G11C11/4076 ,  G11C29/48

CPC classification number: G11C11/4076 ,  G11C29/842

Abstract: A method of accessing a semiconductor memory is disclosed which includes outputting a row address and an active command to the semiconductor memory; outputting a column address and a read or write command to the semiconductor memory; and outputting a spare access command to the semiconductor memory to access data from a spare memory cell at a timing based on an additive latency of the semiconductor memory. Related devices and systems are also disclosed.

Abstract translation: 公开了一种访问半导体存储器的方法，其包括向半导体存储器输出行地址和有效命令; 向半导体存储器输出列地址和读或写命令; 以及基于所述半导体存储器的附加延迟的定时，向所述半导体存储器输出备用访问命令以从备用存储单元访问数据。 还公开了相关的装置和系统。

公开(公告)号：US20150067448A1

公开(公告)日：2015-03-05

申请号：US14305095

申请日：2014-06-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-Pil SON ,  Young-Soo SOHN ,  Uk-Song KANG ,  Chul-Woo PARK ,  Jung-Hwan CHOI ,  Won-Il BAE ,  Kyo-Min SOHN

IPC: G06F11/10 ,  G11C29/52

CPC classification number: G11C29/52 ,  G06F11/1048 ,  G11C2029/0411

Abstract: In a method of operating a memory device, a command and a first address from a memory controller are received. A read code word including a first set of data corresponding to the first address, a second set of data corresponding to a second address and a read parity data is read from a memory cell array of the memory device. Corrected data are generated by operating error checking and correction (ECC) using an ECC circuit based on the read cord word.

Abstract translation: 在操作存储器件的方法中，接收来自存储器控制器的命令和第一地址。 从存储器件的存储单元阵列读取包括对应于第一地址的第一组数据，对应于第二地址的第二组数据和读取奇偶校验数据的读码字。 通过使用基于读取的线字的ECC电路的操作错误检查和校正（ECC）来生成校正的数据。