公开(公告)号：US20160351244A1

公开(公告)日：2016-12-01

申请号：US15236895

申请日：2016-08-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Soo SOHN ,  Chul-Woo PARK ,  Si-Hong KIM ,  KWANG-IL PARK ,  Jae-Youn YOUN

IPC: G11C11/406 ,  G11C11/408 ,  G11C11/4076

CPC classification number: G11C11/406 ,  G11C11/4076 ,  G11C11/4087

Abstract: A memory device includes a memory cell array, an intensively accessed row detection circuit, and a refresh control circuit. The memory cell array includes a plurality of memory cell rows. The intensively accessed row detection circuit generates an intensively accessed row address indicating an intensively accessed memory cell row among the plurality of memory cell rows based on an accumulated access time for each of the plurality of memory cell rows. The refresh control unit preferentially refreshes neighboring memory cell rows adjacent to the intensively accessed memory cell row indicated by the intensively accessed row address when receiving the intensively accessed row address from the intensively accessed row detection unit. The memory device effectively reduces a rate of data loss.

公开(公告)号：US20150243338A1

公开(公告)日：2015-08-27

申请号：US14514416

申请日：2014-10-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Soo SOHN ,  Chul-Woo PARK ,  Si-Hong KIM ,  KWANG-IL PARK ,  Jae-Youn YOUN

IPC: G11C11/406 ,  G11C11/408 ,  G11C11/4076

CPC classification number: G11C11/406 ,  G11C11/4076 ,  G11C11/4087

Abstract: A memory device includes a memory cell array, an intensively accessed row detection circuit, and a refresh control circuit. The memory cell array includes a plurality of memory cell rows. The intensively accessed row detection circuit generates an intensively accessed row address indicating an intensively accessed memory cell row among the plurality of memory cell rows based on an accumulated access time for each of the plurality of memory cell rows. The refresh control unit preferentially refreshes neighboring memory cell rows adjacent to the intensively accessed memory cell row indicated by the intensively accessed row address when receiving the intensively accessed row address from the intensively accessed row detection unit. The memory device effectively reduces a rate of data loss.

Abstract translation: 存储器件包括存储单元阵列，集中访问的行检测电路和刷新控制电路。 存储单元阵列包括多个存储单元行。 集中访问的行检测电路基于多个存储单元行中的每一个的累积访问时间，生成指示多个存储单元行中的集中访问的存储单元行的集中访问的行地址。 当从集中访问的行检测单元接收到集中访问的行地址时，刷新控制单元优先刷新与由强行访问的行地址指示的集中访问的存储单元行相邻的相邻存储单元行。 存储器件有效地降低了数据丢失率。

公开(公告)号：US20150309743A1

公开(公告)日：2015-10-29

申请号：US14588496

申请日：2015-01-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Soo SOHN ,  Uk-Song KANG ,  KWANG-IL PARK ,  Chul-Woo PARK ,  Hak-Soo YU ,  Jae-Youn YOUN

IPC: G06F3/06

CPC classification number: G11C11/4087 ,  G11C5/025 ,  G11C7/02 ,  G11C11/4085

Abstract: A semiconductor memory device includes a control logic and a memory cell array in which a plurality of memory cells are arranged. The memory cell array includes a plurality of bank arrays, and each of the plurality of bank arrays includes a plurality of sub-arrays. The control logic controls an access to the memory cell array based on a command and an address signal. The control logic dynamically sets a keep-away zone that includes a plurality of memory cell rows which are deactivated based on a first word-line when the first word-line is enabled. The first word-line is coupled to a first memory cell row of a first sub-array of the plurality of sub-arrays. Therefore, increased timing parameters may be compensated, and parallelism may be increased.

Abstract translation: 半导体存储器件包括控制逻辑和其中布置有多个存储器单元的存储单元阵列。 存储单元阵列包括多个存储体阵列，并且多个存储体阵列中的每一个包括多个子阵列。 控制逻辑基于命令和地址信号控制对存储器单元阵列的访问。 控制逻辑动态地设置包括在第一字线被启用时基于第一字线被去激活的多个存储器单元行的保留区。 第一字线耦合到多个子阵列中的第一子阵列的第一存储单元行。 因此，可以补偿增加的定时参数，并且可以增加并行性。

公开(公告)号：US20180358060A1

公开(公告)日：2018-12-13

申请号：US15851197

申请日：2017-12-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SANG-UHN CHA ,  YOUNG -HUN SEO ,  KWANG-IL PARK ,  SEUNG-JUN BAE

IPC: G11C7/10 ,  G11C11/4093 ,  G11C11/4096 ,  G06F11/10 ,  H03M13/00

CPC classification number: G11C7/1006 ,  G06F11/1044 ,  G06F11/1048 ,  G11C7/1018 ,  G11C7/106 ,  G11C7/1087 ,  G11C11/4093 ,  G11C11/4096 ,  G11C29/52 ,  G11C2029/0411 ,  H03M13/05 ,  H03M13/611

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, an input/output (I/O) gating circuit and a control logic circuit. The memory cell array includes bank arrays, each of the bank arrays includes a first sub array and a second sub array, and each of the first sub array and the second sub array includes a normal cell region to store data bits and a parity cell region to store parity bits. The ECC engine generates the parity bits and corrects error bit. The I/O gating circuit is connected between the ECC engine and the memory cell array. The control logic circuit controls the I/O gating circuit to perform column access to the normal cell region according to a multiple of a burst length and to perform column access to the parity cell region according to a non-multiple of the burst length partially.