公开(公告)号：US20210005553A1

公开(公告)日：2021-01-07

申请号：US16805890

申请日：2020-03-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： YOUNG KUN JEE ,  HAE-JUNG YU ,  SANGWON KIM ,  UN-BYOUNG KANG ,  JONGHO LEE ,  DAE-WOO KIM ,  WONJAE LEE

IPC: H01L23/538 ,  H01L23/498 ,  H01L25/18

Abstract: A semiconductor package includes a package substrate, a plurality of package terminals disposed on the bottom surface of the package substrate, and an interposer substrate disposed on the top surface of the package substrate, a plurality of interposer terminals disposed on the bottom surface of the interposer substrate and electrically connected to the package substrate, a first semiconductor chip disposed on the top surface of the interposer substrate, a second semiconductor chip disposed on the top surface of the interposer substrate and disposed to be horizontally separated from the first semiconductor chip, a first plurality of signal pads disposed on the top surface of the interposer substrate and electrically connected to wiring in the interposer substrate and one or more circuits in the first semiconductor chip, a second plurality of signal pads disposed on the top surface of the interposer substrate and electrically connected to wiring in the interposer substrate and to one or more circuits in the second semiconductor chip, and a plurality of dummy pads disposed outside of an area occupied by the first semiconductor chip or the second semiconductor chip from a top-down view and disposed on the top surface of the interposer substrate. Each pad of the first plurality of signal pads and the second plurality of signal pads is configured to transfer signals between the interposer substrate and a respective semiconductor chip, and each pad of the dummy pads is not configured to transfer signals between the interposer substrate and any semiconductor chip disposed thereon.

公开(公告)号：US20230170290A1

公开(公告)日：2023-06-01

申请号：US17886872

申请日：2022-08-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： YUN-HEE LEE ,  JAESUN KIM ,  SEOKBEOM YONG ,  WONJAE LEE

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/13 ,  H01L24/29 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/2919 ,  H01L2224/13147 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2924/0665

Abstract: Disclosed is a semiconductor package comprising a redistribution substrate and a semiconductor chip on the redistribution substrate. The redistribution substrate includes a plurality of first conductive patterns including a pair of first signal patterns that are adjacent to each other, and a plurality of second conductive patterns on surfaces of the first conductive patterns and coupled to the first conductive patterns. The second conductive patterns include a ground pattern insulated from the pair of first signal patterns. The ground pattern has an opening that penetrates the ground pattern. When viewed in plan, the pair of first signal patterns overlap the opening.

公开(公告)号：US20230141318A1

公开(公告)日：2023-05-11

申请号：US17879106

申请日：2022-08-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYEONJEONG HWANG ,  DONGKYU KIM ,  KYOUNG LIM SUK ,  WONJAE LEE

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/498

CPC classification number: H01L23/5386 ,  H01L25/0652 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16

Abstract: A redistribution substrate may include a first interconnection layer having a first insulating pattern, a first dummy pattern and a second dummy pattern, the first and second dummy patterns being in the first insulating pattern, and a second interconnection layer stacked on the first interconnection layer, the second interconnection layer having a second insulating pattern, a signal pattern and a power/ground pattern, the signal and power/ground patterns being in the second insulating pattern. The first dummy pattern may be located below the signal pattern, and the second dummy pattern may be located below the power/ground pattern. The first dummy pattern may include dot patterns, and the second dummy pattern may include a plate pattern.

公开(公告)号：US20230142196A1

公开(公告)日：2023-05-11

申请号：US17844802

申请日：2022-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： YONGJIN SEOL ,  SEONHYANG YOU ,  WONJAE LEE ,  WOOIK JANG

IPC: H01L23/66 ,  H01L23/498 ,  H01L23/31 ,  H01L23/29

CPC classification number: H01L23/66 ,  H01L23/49827 ,  H01L23/3107 ,  H01L23/29

Abstract: A semiconductor package includes a package substrate, a semiconductor chip on the package substrate, a mold layer on the package substrate to cover the semiconductor chip, the mold layer having a first side surface and a first trench disposed at the first side surface, and the first trench extending from a top surface of the mold layer toward a bottom surface of the mold layer, an antenna pattern on the mold layer, and a first connection terminal filling the first trench. The antenna pattern is electrically connected to the package substrate through the first connection terminal.

公开(公告)号：US20220173044A1

公开(公告)日：2022-06-02

申请号：US17674900

申请日：2022-02-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： YOUNG KUN JEE ,  HAE-JUNG YU ,  SANGWON KIM ,  UN-BYOUNG KANG ,  JONGHO LEE ,  DAE-WOO KIM ,  WONJAE LEE

IPC: H01L23/538 ,  H01L25/18 ,  H01L23/498

Abstract: A semiconductor package includes a package substrate, a plurality of package terminals disposed on the bottom surface of the package substrate, and an interposer substrate disposed on the top surface of the package substrate, a plurality of interposer terminals disposed on the bottom surface of the interposer substrate and electrically connected to the package substrate, a first semiconductor chip disposed on the top surface of the interposer substrate, a second semiconductor chip disposed on the top surface of the interposer substrate and disposed to be horizontally separated from the first semiconductor chip, a first plurality of signal pads disposed on the top surface of the interposer substrate and electrically connected to wiring in the interposer substrate and one or more circuits in the first semiconductor chip, a second plurality of signal pads disposed on the top surface of the interposer substrate and electrically connected to wiring in the interposer substrate and to one or more circuits in the second semiconductor chip, and a plurality of dummy pads disposed outside of an area occupied by the first semiconductor chip or the second semiconductor chip from a top-down view and disposed on the top surface of the interposer substrate. Each pad of the first plurality of signal pads and the second plurality of signal pads is configured to transfer signals between the interposer substrate and a respective semiconductor chip, and each pad of the dummy pads is not configured to transfer signals between the interposer substrate and any semiconductor chip disposed thereon.