-
公开(公告)号：US20240147722A1
公开(公告)日：2024-05-02
申请号：US18331397
申请日：2023-06-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Byongju Kim , Dongsung Choi , Wonjun Park , Donghwa Lee , Jaemin Jung , Changheon Cheon
IPC: H10B43/27 , H01L23/528 , H01L25/065 , H10B41/10 , H10B41/27 , H10B41/35 , H10B43/10 , H10B43/35 , H10B80/00
CPC classification number: H10B43/27 , H01L23/5283 , H01L25/0652 , H10B41/10 , H10B41/27 , H10B41/35 , H10B43/10 , H10B43/35 , H10B80/00 , H01L2225/06551
Abstract: A semiconductor device may include a gate stack that includes a first insulating pattern, a second insulating pattern adjacent to the first insulating pattern, a third insulating pattern adjacent to the second insulating pattern, a first conductive pattern between the first and second insulating patterns, and a second conductive pattern between the second and third insulating patterns, a channel layer that extends in the gate stack, a tunnel insulating layer on the channel layer, and a first data storage pattern and a second data storage pattern on the tunnel insulating layer. The first data storage pattern may include a first outer portion between the first and second insulating patterns, and a first inner portion on the first outer portion.
-
公开(公告)号：US11574956B2
公开(公告)日：2023-02-07
申请号：US17314638
申请日：2021-05-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jiho Park , Kwangmin Park , Wonjun Park , Jeonghee Park , Changyup Park , Hwasung Chae
Abstract: A semiconductor device includes a substrate; first conductive lines extending in a first direction; second conductive lines extending in a second direction; memory cell structures between the first conductive lines and the second conductive lines; and dummy cell structures that are electrically isolated and between the first conductive lines and the second conductive lines. The memory cell structures include a data storage material pattern including a phase change material layer; and a selector material pattern overlapping the data storage material pattern in a vertical direction. The dummy cell structures include a dummy pattern including a phase change material layer. The phase change material layer of the dummy pattern includes a crystalline phase portion and an amorphous phase portion. At a cross section of the phase change material layer of the dummy pattern, an area of the crystalline phase portion is larger than an area of the amorphous phase portion.
-
公开(公告)号：US12232429B2
公开(公告)日：2025-02-18
申请号：US17384933
申请日：2021-07-26
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jeonghee Park , Dongho Ahn , Wonjun Park
Abstract: A semiconductor device includes a first conductive line on a lower structure and extending in a first horizontal direction; a second conductive line on the first conductive line and extending in a second horizontal direction, the second horizontal direction being perpendicular to the first horizontal direction; and a memory cell structure between the first conductive line and the second conductive line. The memory cell may structure include a data storage material pattern and a selector material pattern overlapping the data storage material pattern in a vertical direction. The data storage material pattern may include a phase change material layer of InαGeβSbγTeδ. In the phase change material layer of InαGeβSbγTeδ, a sum of α and β may be lower than about 30 at. %, and a sum of γ and δ may be higher than about 70 at. %.
-
Patent Agency Ranking
公开(公告)号：US12185647B2
公开(公告)日：2024-12-31
申请号：US18119970
申请日：2023-03-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Wonjun Park , Chungman Kim , Dongho Ahn , Changyup Park
Abstract: A variable resistance memory device includes a first conductive line extending on a substrate in a first horizontal direction; a second conductive line extending on the first conductive line in a second horizontal direction perpendicular to the first horizontal direction; and a memory cell at an intersection between the first conductive line and the second conductive line, the memory cell including a selection element and a variable resistor, wherein the variable resistor includes a first variable resistance layer having a senary component represented by CaGebSbcTedAeXf, in which A and X are each a group 13 element different from each other, and 1≤a≤18, 13≤b≤26, 15≤c≤30, 35≤d≤55, 0.1≤e≤8, 0.1≤f≤8, and a+b+c+d+e+f=100.
-
公开(公告)号：US20240224523A1
公开(公告)日：2024-07-04
申请号：US18493853
申请日：2023-10-25
Applicant: Samsung Electronics Co., Ltd.
Inventor： Dongsung Choi , Byongju Kim , Wonjun Park , Jaemin Jung , Changheon Cheon
Abstract: A non-volatile memory device includes a substrate, a mold structure including a plurality of gate electrodes and a plurality of mold insulating layers, wherein the plurality of gate electrodes are stacked in a step shape, a channel structure that extends through the mold structure, and a cell contact that extends through the mold structure, the cell contact is connected to a first gate electrode, and the cell contact is not electrically connected to a second gate electrode among the plurality of gate electrodes, wherein the first gate electrode includes: an extension portion; a pad portion having a vertical thickness greater than a vertical thickness of the extension portion; and a connection portion that electrically connects the pad portion to the cell contact, the connection portion has a vertical thickness less than a vertical thickness of the pad portion, and one or more first insulating rings on the connection portion.
-
公开(公告)号：US20240074195A1
公开(公告)日：2024-02-29
申请号：US18308262
申请日：2023-04-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Byongju Kim , Dongsung Choi , Wonjun Park , Donghwa Lee , Jaemin Jung , Changheon Cheon
Abstract: A semiconductor device includes a conductive pattern, an insulating pattern, a channel film extending in a vertical direction inside a channel hole, a charge trap pattern between the conductive pattern and the channel film inside the channel hole, a tunneling dielectric film between the charge trap pattern and the channel film, and a blocking dielectric film extending between the conductive pattern and the charge trap pattern and between the insulating pattern and the tunneling dielectric film. The insulating pattern includes a first insulating pattern overlapping the conductive pattern in the vertical direction and a second insulating pattern protruding in the lateral direction from the first insulating pattern into the channel hole and toward the channel film. The first insulating pattern has a first dielectric constant, and the second insulating pattern has a second dielectric constant that is lower than the first dielectric constant.
-
公开(公告)号：US20230165174A1
公开(公告)日：2023-05-25
申请号：US17938200
申请日：2022-10-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Changyup Park , Dongho Ahn , Donggeon Gu , Wonjun Park , Jinwoo Lee
CPC classification number: H01L45/128 , H01L27/2454 , H01L45/06 , H01L45/124 , H01L45/144 , H01L45/1253
Abstract: A semiconductor device includes gate electrodes on a substrate, a channel and a resistance pattern. The gate electrodes are spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate. The channel extends through the gate electrodes in the vertical direction on the substrate. The resistance pattern includes a phase-changeable material. The resistance pattern includes a first vertical extension portion on a sidewall of the channel and extending in the vertical direction, a first protrusion portion on an inner sidewall of the first vertical extension portion and protruding in a horizontal direction substantially parallel to the upper surface of the substrate, and a second protrusion portion on an outer sidewall of the first vertical extension portion and protruding in the horizontal direction and not overlapping the first protrusion portion in the horizontal direction.
-
公开(公告)号：US20220085105A1
公开(公告)日：2022-03-17
申请号：US17314638
申请日：2021-05-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jiho Park , Kwangmin Park , Wonjun Park , Jeonghee Park , Changyup Park , Hwasung Chae
Abstract: A semiconductor device includes a substrate; first conductive lines extending in a first direction; second conductive lines extending in a second direction; memory cell structures between the first conductive lines and the second conductive lines; and dummy cell structures that are electrically isolated and between the first conductive lines and the second conductive lines. The memory cell structures include a data storage material pattern including a phase change material layer; and a selector material pattern overlapping the data storage material pattern in a vertical direction. The dummy cell structures include a dummy pattern including a phase change material layer. The phase change material layer of the dummy pattern includes a crystalline phase portion and an amorphous phase portion. At a cross section of the phase change material layer of the dummy pattern, an area of the crystalline phase portion is larger than an area of the amorphous phase portion.
-
-
-
-
-
-
-
Search Results
8
records
(took 0.019 seconds)
