公开(公告)号：US20240055406A1

公开(公告)日：2024-02-15

申请号：US18364802

申请日：2023-08-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeongseon Kim ,  Dohyun Kim ,  Juhyeon Kim ,  Hyoeun Kim ,  Seonkyung Seo ,  Chajea Jo

IPC: H01L25/065 ,  H01L25/10 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L25/105 ,  H01L23/3107 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2224/0384 ,  H01L2224/039 ,  H01L2224/05014 ,  H01L2224/05015 ,  H01L2224/05541 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/08121 ,  H01L2224/08148 ,  H01L2224/08235 ,  H01L2224/80203 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/38

Abstract: A semiconductor package includes a first semiconductor chip including a first semiconductor device, a second semiconductor chip including a second semiconductor device, and a bonding structure between the first and second semiconductor chips, the bonding structure including a first bonding pad, a first bonding insulating layer, a second bonding pad in contact with the first bonding pad, and a second bonding insulating layer in contact with the first bonding insulating layer. The first bonding pad may include a first pad metal layer and a first conductive barrier layer surrounding the first pad metal layer, and the first conductive barrier layer may include a horizontal extension portion extending on an edge of an upper surface of the first pad metal layer.

公开(公告)号：US20240387483A1

公开(公告)日：2024-11-21

申请号：US18493041

申请日：2023-10-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juhyeon Kim ,  Yeongseon Kim ,  Sunkyoung Seo

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498

Abstract: A semiconductor package may include a redistribution substrate, a first lower semiconductor chip on the redistribution substrate, an upper semiconductor chip on the first lower semiconductor chip, and a first insulating element between the redistribution substrate and the upper semiconductor chip to enclose the first lower semiconductor chip. The first lower semiconductor chip may include a first pad on a first surface of the first lower semiconductor chip, a first protection layer enclosing the first pad, a first penetration via that penetrates the first lower semiconductor chip and is electrically connected to the first pad, a second pad on a second surface of the first lower semiconductor chip facing the upper semiconductor chip, and a first insulating layer including the second pad. A particle size of a material including the first protection layer may be smaller than that of the first insulating element.

公开(公告)号：US20250029879A1

公开(公告)日：2025-01-23

申请号：US18765816

申请日：2024-07-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongkuk Lee ,  Yeongseon Kim

IPC: H01L21/66 ,  H01L23/00 ,  H01L23/48 ,  H01L25/065

Abstract: Disclosed is a semiconductor package comprising a first semiconductor chip and a second semiconductor chip on the first semiconductor chip. The first semiconductor chip may include an upper bonding pad, an upper test pad, and an upper dielectric layer that surrounds the upper bonding pad and the upper test pad. The second semiconductor chip includes a lower bonding pad in contact with the upper bonding pad, a lower test pad in contact with the upper test pad, and a lower dielectric layer that surrounds the lower bonding pad and the lower test pad.