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公开(公告)号：US20240321857A1
公开(公告)日：2024-09-26
申请号：US18736766
申请日：2024-06-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Juhyeon Kim , Hyoeun Kim , Sunkyoung Seo
IPC: H01L25/00 , H01L21/768 , H01L21/78 , H01L23/00 , H01L25/065
CPC classification number: H01L25/50 , H01L21/76898 , H01L21/78 , H01L24/03 , H01L24/80 , H01L24/94 , H01L24/97 , H01L24/08 , H01L24/13 , H01L25/0657 , H01L2224/0401 , H01L2224/08146 , H01L2224/80001 , H01L2225/06541
Abstract: A method of manufacturing a semiconductor package includes preparing a wafer structure having a first semiconductor substrate and a plurality of first front surface connection pads. A lower semiconductor chip having a preliminary semiconductor substrate and a plurality of second front surface connection pads are attached to the wafer structure such that the plurality of first front surface connection pads and the plurality of second front surface connection pads correspond to each other. A plurality of bonding pads is formed by bonding together the plurality of first front surface connection pads and the plurality of second front surface connection pads corresponding to each other. A second semiconductor substrate having a horizontal width that is less than that of the second wiring structure is formed by removing a portion of the preliminary semiconductor substrate.
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公开(公告)号：US20230013176A1
公开(公告)日：2023-01-19
申请号：US17656011
申请日：2022-03-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Juhyeon Kim , Hyoeun Kim , Sunkyoung Seo
IPC: H01L25/00 , H01L23/00 , H01L21/768 , H01L21/78
Abstract: A method of manufacturing a semiconductor package includes preparing a wafer structure having a first semiconductor substrate and a plurality of first front surface connection pads. A lower semiconductor chip having a preliminary semiconductor substrate and a plurality of second front surface connection pads are attached to the wafer structure such that the plurality of first front surface connection pads and the plurality of second front surface connection pads correspond to each other. A plurality of bonding pads is formed by bonding together the plurality of first front surface connection pads and the plurality of second front surface connection pads corresponding to each other. A second semiconductor substrate having a horizontal width that is less than that of the second wiring structure is formed by removing a portion of the preliminary semiconductor substrate.
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公开(公告)号：US20240387483A1
公开(公告)日：2024-11-21
申请号：US18493041
申请日：2023-10-24
Applicant: Samsung Electronics Co., Ltd.
Inventor： Juhyeon Kim , Yeongseon Kim , Sunkyoung Seo
IPC: H01L25/10 , H01L23/00 , H01L23/31 , H01L23/48 , H01L23/498
Abstract: A semiconductor package may include a redistribution substrate, a first lower semiconductor chip on the redistribution substrate, an upper semiconductor chip on the first lower semiconductor chip, and a first insulating element between the redistribution substrate and the upper semiconductor chip to enclose the first lower semiconductor chip. The first lower semiconductor chip may include a first pad on a first surface of the first lower semiconductor chip, a first protection layer enclosing the first pad, a first penetration via that penetrates the first lower semiconductor chip and is electrically connected to the first pad, a second pad on a second surface of the first lower semiconductor chip facing the upper semiconductor chip, and a first insulating layer including the second pad. A particle size of a material including the first protection layer may be smaller than that of the first insulating element.
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公开(公告)号：US11444060B2
公开(公告)日：2022-09-13
申请号：US16742341
申请日：2020-01-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sanguk Han , Chajea Jo , Hyoeun Kim , Sunkyoung Seo
IPC: H01L25/065 , H01L23/00 , H01L23/31
Abstract: A package-on-package type package includes a lower semiconductor package and an upper semiconductor package. The lower semiconductor package includes a first semiconductor device including a through electrode, a second semiconductor device disposed on the first semiconductor device and including a second through electrode electrically connected to the first through electrode, a first molding member covering a sidewall of at least one of the first semiconductor device and the second semiconductor device, a second molding member covering a sidewall of the first molding member, and an upper redistribution layer disposed on the second semiconductor device and electrically connected to the second through electrode.
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公开(公告)号：US11328966B2
公开(公告)日：2022-05-10
申请号：US16749620
申请日：2020-01-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyoeun Kim , Yonghoe Cho , Sunkyoung Seo , Seunghoon Yeon , Sanguk Han
Abstract: A chip-stacked semiconductor package includes a first chip including a first detection pad and a second detection pad; a second chip provided on the first chip, the second chip including a third detection pad facing the first detection pad and a fourth detection pad facing the second detection pad; and a first medium provided between the first detection pad and the third detection pad to connect the first detection pad to the third detection pad through the first medium, and a second medium, different from the first medium, provided between the second detection pad and the fourth detection pad to connect the second detection pad to the fourth detection pad through the second medium.
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Patent Agency Ranking
公开(公告)号：US20250022828A1
公开(公告)日：2025-01-16
申请号：US18609921
申请日：2024-03-19
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyoeun Kim , Haksun Lee , Dohyun Kim , Sunkyoung Seo , Chajea Jo
Abstract: The present disclosure relates to semiconductor packages and methods of fabricating the semiconductor packages. An example semiconductor package includes a first semiconductor die including a first substrate and a first bonding layer on the first substrate, a second semiconductor die disposed on the first semiconductor die, the second semiconductor die including a second substrate and a second bonding layer under the second substrate, and a silicon oxide layer interposed between the first semiconductor die and the second semiconductor die, where at least one pore is disposed in the silicon oxide layer, and the at least one pore has a height of 1 Å to 2 nm.
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公开(公告)号：US12087696B2
公开(公告)日：2024-09-10
申请号：US18095900
申请日：2023-01-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sunkyoung Seo , Taehwan Kim , Hyunjung Song , Hyoeun Kim , Wonil Lee , Sanguk Han
IPC: H01L23/48 , H01L23/00 , H01L23/367 , H01L23/538
CPC classification number: H01L23/5384 , H01L23/367 , H01L23/5385 , H01L23/5386 , H01L24/14
Abstract: A semiconductor package includes a package substrate, a lower semiconductor device arranged on the package substrate and including first through electrodes, first lower connection bumps arranged between the package substrate and the lower semiconductor device and electrically connecting the package substrate to the first through electrodes, a connecting substrate arranged on the package substrate and including second through electrodes, second lower connection bumps arranged between the package substrate and the connecting substrate and electrically connecting the package substrate to the second through electrodes, and an upper semiconductor device arranged on the lower semiconductor device and electrically connected to the first through electrodes and the second through electrodes.
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公开(公告)号：US11923342B2
公开(公告)日：2024-03-05
申请号：US17705872
申请日：2022-03-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sanguk Han , Chajea Jo , Hyoeun Kim , Sunkyoung Seo
IPC: H01L25/065 , H01L23/00 , H01L23/31
CPC classification number: H01L25/0657 , H01L23/3121 , H01L23/3135 , H01L24/13
Abstract: A package-on-package type package includes a lower semiconductor package and an upper semiconductor package. The lower semiconductor package includes a first semiconductor device including a through electrode, a second semiconductor device disposed on the first semiconductor device and including a second through electrode electrically connected to the first through electrode, a first molding member covering a sidewall of at least one of the first semiconductor device and the second semiconductor device, a second molding member covering a sidewall of the first molding member, and an upper redistribution layer disposed on the second semiconductor device and electrically connected to the second through electrode.
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公开(公告)号：US20230207532A1
公开(公告)日：2023-06-29
申请号：US18176058
申请日：2023-02-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Joonho JUN , Un-Byoung Kang , Sunkyoung Seo , Jongho Lee , Young Kun Jee
IPC: H01L25/065 , H01L23/00
CPC classification number: H01L25/0657 , H01L24/14 , H01L24/06 , H01L2224/06181 , H01L2224/1451 , H01L2224/06515 , H01L2224/0401 , H01L2225/06513
Abstract: A semiconductor package may include first and second substrates, which are vertically stacked, a semiconductor device layer on a bottom surface of the second substrate to face a top surface of the first substrate, upper chip pads and an upper dummy pad on the top surface of the first substrate, penetration electrodes, which each penetrate the first substrate and are connected to separate, respective upper chip pads, lower chip pads on a bottom surface of the semiconductor device layer and electrically connected to separate, respective upper chip pads, and a lower dummy pad on the bottom surface of the semiconductor device layer and electrically isolated from the upper dummy pad. A distance between the upper and lower dummy pads in a horizontal direction that is parallel to the first substrate may be smaller than a diameter of the lower dummy pad.
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公开(公告)号：US11574873B2
公开(公告)日：2023-02-07
申请号：US17003639
申请日：2020-08-26
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sunkyoung Seo , Taehwan Kim , Hyunjung Song , Hyoeun Kim , Wonil Lee , Sanguk Han
IPC: H01L23/367 , H01L23/538 , H01L23/00
Abstract: A semiconductor package includes a package substrate, a lower semiconductor device arranged on the package substrate and including first through electrodes, first lower connection bumps arranged between the package substrate and the lower semiconductor device and electrically connecting the package substrate to the first through electrodes, a connecting substrate arranged on the package substrate and including second through electrodes, second lower connection bumps arranged between the package substrate and the connecting substrate and electrically connecting the package substrate to the second through electrodes, and an upper semiconductor device arranged on the lower semiconductor device and electrically connected to the first through electrodes and the second through electrodes.
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