公开(公告)号：US09252123B2

公开(公告)日：2016-02-02

申请号：US14505802

申请日：2014-10-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Won-Gil Han ,  Se-Yeoul Park ,  Ho-Tae Jin ,  Byong-Joo Kim ,  Yong-Je Lee ,  Han-Ki Park

IPC: H01L23/00 ,  H01L21/66 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L24/85 ,  H01L22/14 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/78 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/4847 ,  H01L2224/48992 ,  H01L2224/4941 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/8503 ,  H01L2224/85951 ,  H01L2224/92247 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/35 ,  H01L2924/00012 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A multi-chip package may include a first semiconductor chip, a second semiconductor chip, a first stud bump, a first nail head bonding bump, a second stud bump, and a first conductive wire. The first semiconductor chip may have a first bonding pad. The second semiconductor chip may be stacked on the first semiconductor chip so the first bonding pad remains exposed. The second semiconductor chip may have a second bonding pad. The first stud bump may be formed on the first bonding pad. The first nail head bonding bump may be formed on the first stud bump, with one end of a first conductive wire formed between the two. The second stud bump may be formed on the second bonding pad, with another end of the first conductive wire formed between the two. An electrical connection test may be performed on each of the wire bonding processes.

Abstract translation: 多芯片封装可以包括第一半导体芯片，第二半导体芯片，第一螺柱凸块，第一钉头结合凸块，第二凸柱凸块和第一导线。 第一半导体芯片可以具有第一接合焊盘。 第二半导体芯片可以堆叠在第一半导体芯片上，使得第一焊盘保持暴露。 第二半导体芯片可以具有第二接合焊盘。 可以在第一接合焊盘上形成第一螺柱凸块。 第一钉头结合凸块可以形成在第一凸起凸起上，其中一个第一导线形成在两者之间。 可以在第二接合焊盘上形成第二螺柱凸块，其中第一导线的另一端形成在两者之间。 可以在每个引线接合工艺上执行电连接测试。

公开(公告)号：US10147706B2

公开(公告)日：2018-12-04

申请号：US15623891

申请日：2017-06-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Won-Gil Han ,  Byong-Joo Kim ,  Yong-Je Lee ,  Jae-Heung Lee ,  Seung-Weon Ha

IPC: H01L25/065 ,  H01L23/00

Abstract: A multi-chip package includes a package substrate including a first substrate pad, a first group of semiconductor chips stacked on the package substrate, each of the first group of the semiconductor chips including bonding pads, first stud bumps arranged on the bonding pads of the first group of the semiconductor chips except for a lowermost semiconductor chip in the first group, a first conductive wire downwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and connected to the first substrate pad, and a second conductive wire upwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and sequentially connected to the first stud bumps.

公开(公告)号：US10784244B2

公开(公告)日：2020-09-22

申请号：US16177968

申请日：2018-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Won-Gil Han ,  Seung-Lo Lee ,  Yong-Je Lee ,  Sung-Il Cho

IPC: H01L25/18 ,  H01L23/00 ,  H01L25/00

Abstract: A semiconductor package includes a package substrate, at least one first semiconductor chip on the package substrate and having a first height as measured from the package substrate, at least one second semiconductor chip on the package substrate spaced apart from the first semiconductor chip and having a second height less than the first height as measured from the package substrate, at least one third semiconductor chip stacked on the first and second semiconductor chips, and at least one support structure between the at least one second semiconductor chip and the at least one third semiconductor chip configured to support the at least one third semiconductor chip.

公开(公告)号：US10679972B2

公开(公告)日：2020-06-09

申请号：US16193318

申请日：2018-11-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Won-Gil Han ,  Byong-Joo Kim ,  Yong-Je Lee ,  Jae-Heung Lee ,  Seung-Weon Ha

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

Abstract: A multi-chip package includes a package substrate including a first substrate pad, a first group of semiconductor chips stacked on the package substrate, each of the first group of the semiconductor chips including bonding pads, first stud bumps arranged on the bonding pads of the first group of the semiconductor chips except for a lowermost semiconductor chip in the first group, a first conductive wire downwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and connected to the first substrate pad, and a second conductive wire upwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and sequentially connected to the first stud bumps.