公开(公告)号：US10790168B2

公开(公告)日：2020-09-29

申请号：US15972350

申请日：2018-05-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Bo Shim ,  Hyuk Kim ,  Sun Taek Lim ,  Jae Myung Choe ,  Jeon Il Lee ,  Sung-Il Cho

IPC: H01L21/67 ,  H01L21/683 ,  H01J37/32 ,  H01L21/3065 ,  H01L21/311

Abstract: Provided are a plasma treatment apparatus and a method of fabricating semiconductor device using the same. The plasma treatment apparatus includes a chamber which provides a plasma treatment space, a bottom electrode disposed in the chamber and supports a wafer, a top electrode disposed in the chamber facing the bottom electrode, a source power source which supplies a source power output of a first frequency to the bottom electrode, a bias power source which supplies a bias power output of a second frequency different from the first frequency to the bottom electrode, and a pulse power source which applies a pulse voltage to the bottom electrode, wherein the bias power output is a bias voltage which is pulse-modulated to a first voltage level in a first time section and pulse-modulated to a second voltage level in a second time section and is applied to the bottom electrode.

公开(公告)号：US10784244B2

公开(公告)日：2020-09-22

申请号：US16177968

申请日：2018-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Won-Gil Han ,  Seung-Lo Lee ,  Yong-Je Lee ,  Sung-Il Cho

IPC: H01L25/18 ,  H01L23/00 ,  H01L25/00

Abstract: A semiconductor package includes a package substrate, at least one first semiconductor chip on the package substrate and having a first height as measured from the package substrate, at least one second semiconductor chip on the package substrate spaced apart from the first semiconductor chip and having a second height less than the first height as measured from the package substrate, at least one third semiconductor chip stacked on the first and second semiconductor chips, and at least one support structure between the at least one second semiconductor chip and the at least one third semiconductor chip configured to support the at least one third semiconductor chip.

公开(公告)号：US10410990B2

公开(公告)日：2019-09-10

申请号：US15937984

申请日：2018-03-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Man-Hee Han ,  Dae-Sang Chan ,  Sung-Il Cho ,  Jung-Lae Jung

IPC: H01L23/00 ,  B23K1/00 ,  B23K1/005 ,  B23K3/08 ,  B23K101/40

Abstract: A jig for bonding a semiconductor chip may include a pressurizing portion and at least one opening. The pressuring portion may be configured to pressurize an upper surface of the semiconductor chip bonded to a package substrate via a bump and a flux using a laser. The opening may be surrounded by the pressurizing portion. The laser irradiated to the bump and the flux may be transmitted through the opening. A vapor generated from the flux by the laser may be discharged through the opening. Thus, the contamination of the jig caused by the vapor may be prevented so that a transmissivity of the laser through the jig may be maintained.

公开(公告)号：US20190259742A1

公开(公告)日：2019-08-22

申请号：US16177968

申请日：2018-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Won-Gil Han ,  Seung-Lo Lee ,  Yong-je Lee ,  Sung-Il Cho

IPC: H01L25/18 ,  H01L23/00 ,  H01L25/00

Abstract: A semiconductor package includes a package substrate, at least one first semiconductor chip on the package substrate and having a first height as measured from the package substrate, at least one second semiconductor chip on the package substrate spaced apart from the first semiconductor chip and having a second height less than the first height as measured from the package substrate, at least one third semiconductor chip stacked on the first and second semiconductor chips, and at least one support structure between the at least one second semiconductor chip and the at least one third semiconductor chip configured to support the at least one third semiconductor chip.

公开(公告)号：US09786600B2

公开(公告)日：2017-10-10

申请号：US14970160

申请日：2015-12-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Il Cho ,  Nam-Gun Kim ,  Jin-Young Kim ,  Hyun-Chul Yoon ,  Bong-Soo Kim ,  Kwan-Sik Cho

IPC: H01L27/00 ,  H01L29/00 ,  H01L23/00 ,  H01L23/528 ,  H01L29/423 ,  H01L29/78 ,  H01L27/105 ,  H01L29/45 ,  H01L23/535 ,  H01L29/06 ,  H01L27/108

CPC classification number: H01L23/528 ,  H01L23/535 ,  H01L27/1052 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/0649 ,  H01L29/42324 ,  H01L29/45 ,  H01L29/78 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active region of the semiconductor substrate in the cell area, a word line disposed within the semiconductor substrate in the cell area, a bit line contact plug disposed on the cell active region, a bit line disposed on the bit line contact plug, a peripheral insulating isolation region delimiting a peripheral active region of the semiconductor substrate in the peripheral area, and a peripheral transistor including a peripheral transistor lower electrode and a peripheral transistor upper electrode. The bit line contact plug is formed at the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode is formed at the same level in the semiconductor device as the peripheral transistor upper electrode.

公开(公告)号：US09500599B2

公开(公告)日：2016-11-22

申请号：US14603809

申请日：2015-01-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youn-Jo Mun ,  Hoon Sohn ,  Sang-Young Kim ,  Yun-Kyu An ,  Sung-Il Cho ,  Seung-Weon Ha ,  Jin-Yeol Yang ,  Soon-Kyu Hwang

IPC: G01N21/95 ,  G01J5/10 ,  G01J5/08 ,  H04N5/33 ,  G01J5/00

CPC classification number: G01N21/9501 ,  G01J5/0007 ,  G01J5/025 ,  G01J5/026 ,  G01J5/047 ,  G01J5/0803 ,  G01J5/0806 ,  G01J5/0831 ,  G01J5/0896 ,  G01J5/10 ,  G01J2005/0048 ,  G01J2005/0051 ,  G01J2005/0077 ,  G01J2005/0081 ,  G01N2201/06113 ,  H04N5/33

Abstract: A surface inspection apparatus and method of inspecting chip surfaces includes a laser generator that generates a periodic CW laser and is transformed into an inspection laser beam having a beam size smaller than a surface size of the chip. Thus, the inspection laser beam is irradiated onto a plurality of the semiconductor chips such that the semiconductor chips are partially and simultaneously heated. Thermal waves are detected in response to the inspection laser beam and thermal images are generated corresponding to the thermal waves. A surface image is generated by a lock-in thermography technique and hold exponent analysis of the thermal image, thereby generating surface image in which a surface defect is included. Time and accuracy of the surface inspection process is improved.

Abstract translation: 表面检查装置和检查芯片表面的方法包括产生周期性CW激光并被转换成具有小于芯片的表面尺寸的光束尺寸的检查激光束的激光发生器。 因此，将检查激光束照射到多个半导体芯片上，使得半导体芯片被部分同时加热。 响应于检查激光束检测热波，并且对应于热波产生热图像。 通过锁定热成像技术产生表面图像，并保持热图像的指数分析，从而产生其中包括表面缺陷的表面图像。 表面检查过程的时间和精度得到提高。