公开(公告)号：US20250142835A1

公开(公告)日：2025-05-01

申请号：US18927200

申请日：2024-10-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yunseong LEE ,  Sijung YOO ,  Seunggeol NAM ,  Kihong KIM ,  Yoonsang PARK ,  Sanghyun JO

IPC: H10B51/30 ,  H10B51/20

Abstract: A semiconductor device, a memory device, and a method of manufacturing the semiconductor device are disclosed. The semiconductor device includes a semiconductor substrate, a ferroelectric layer provided on the semiconductor substrate, an aluminum oxide layer provided on the ferroelectric layer, and a gate electrode provided on the aluminum oxide layer, wherein the aluminum oxide layer includes aluminum, oxygen, and hydrogen, and wherein a content of oxygen in the aluminum oxide layer is more than about 1.5 times and about 2 times or less a content of aluminum in the aluminum oxide layer.

公开(公告)号：US20240260274A1

公开(公告)日：2024-08-01

申请号：US18414933

申请日：2024-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dukhyun CHOE ,  Jinseong HEO ,  Hyunjae LEE ,  Seunggeol NAM ,  Yoonsang PARK ,  Sijung YOO

IPC: H10B51/20 ,  H01L21/28 ,  H01L29/51 ,  H01L29/78 ,  H10B53/20

CPC classification number: H10B51/20 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/78391 ,  H10B53/20

Abstract: Provided are a memory device implementing multi-bit functionality and a memory apparatus including the memory device. The memory device includes a semiconductor substrate, a gate electrode on the semiconductor substrate, and a plurality of ferroelectric layers laminated between the semiconductor substrate and the gate electrode in a first direction perpendicular to a surface of the semiconductor substrate and including at least one first ferroelectric layer and at least one second ferroelectric layer. The first ferroelectric layer has a doping concentration gradient in which a doping concentration increases in the first direction, and the second ferroelectric layer has a doping concentration gradient in which a doping concentration decreases in the first direction. The memory device is configured to implement multi-bit functionality according to an operating voltage.