公开(公告)号：US20240266445A1

公开(公告)日：2024-08-08

申请号：US18638923

申请日：2024-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinseong HEO ,  Taehwan MOON ,  Hagyoul BAE ,  Seunggeol NAM ,  Sangwook KIM ,  Kwanghee LEE

IPC: H01L29/86 ,  H10B69/00 ,  H10K10/50 ,  H10K19/00

CPC classification number: H01L29/86 ,  H10B69/00 ,  H10K10/50 ,  H10K19/00 ,  H10K19/201

Abstract: A semiconductor apparatus includes a plurality of semiconductor devices. The semiconductor devices each include a ferroelectric layer, a conductive metal oxide layer, and a semiconductor layer, between two electrodes. The conductive metal oxide layer may be between the ferroelectric layer and the semiconductor layer. The ferroelectric layer, the conductive metal oxide layer, and the semiconductor layer may all include a metal oxide. The conductive metal oxide layer may include one or more materials selected from the group consisting of an indium oxide, a zinc oxide, a tin oxide, and any combination thereof.

公开(公告)号：US20240265967A1

公开(公告)日：2024-08-08

申请号：US18621853

申请日：2024-03-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunggeol NAM ,  Jinseong HEO ,  Taehwan MOON ,  Hagyoul BAE

IPC: G11C15/04

CPC classification number: G11C15/046

Abstract: Disclosed are a non-volatile content addressable memory device having a simple cell configuration and/or an operating method thereof. The non-volatile content addressable memory device includes a plurality of unit cells, wherein each of the plurality of unit cells consists of or includes a first ferroelectric transistor and a second ferroelectric transistor The first and second ferroelectric transistors are of different types such as different electrical types from each other. The first and second ferroelectric transistors may be connected in series or in parallel to each other. The first and second ferroelectric transistors may share one word line and one match line. The first and second ferroelectric transistors may share one search line. One of the first and second ferroelectric transistors may be connected to a search line and the other one may be connected to a bar search line. The first and second ferroelectric transistors may share one match line.

公开(公告)号：US20230141173A1

公开(公告)日：2023-05-11

申请号：US17983856

申请日：2022-11-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunggeol NAM ,  Hagyoul BAE ,  Jinseong HEO

IPC: H01L29/78 ,  H01L27/118 ,  H01L29/49 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/78391 ,  H01L27/11807 ,  H01L29/4908 ,  H01L29/42392 ,  H01L29/78645 ,  H01L29/78696 ,  H01L2027/11838

Abstract: According to various example embodiments, a semiconductor element includes: a channel layer including a semiconductor material; a p-type semiconductor layer and an n-type semiconductor layer apart from each other with the channel layer therebetween, a paraelectric layer on a first area of the channel layer, a ferroelectric layer on a second area different from the first area of the channel area, and having a polarization state due to a voltage applied from an external source, a first gate electrode on the paraelectric layer, a second gate electrode on the ferroelectric layer, and an insulating layer between the first gate electrode and the second gate electrode, and electrically separating the first gate electrode and the second gate electrode from each other.

公开(公告)号：US20230088827A1

公开(公告)日：2023-03-23

申请号：US17945538

申请日：2022-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunggeol NAM ,  Hyunjae LEE ,  Dukhyun CHOE ,  Jinseong HEO

IPC: H01L29/51 ,  H01L29/78

Abstract: A semiconductor device includes: a first source/drain region; a second source/drain region; a channel between the first source/drain region and the second source/drain region; an interfacial insulating layer on the channel; a ferroelectric layer on the interfacial insulating layer; and a gate electrode on the ferroelectric layer, wherein, when a numerical value of dielectric constant of the interfacial insulating layer is K and a numerical value of remnant polarization of the ferroelectric layer is Pr, a material of the interfacial insulating layer and a material of the ferroelectric layer are selected so that K/Pr is 1 or more.

公开(公告)号：US20220173255A1

公开(公告)日：2022-06-02

申请号：US17461034

申请日：2021-08-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinseong HEO ,  Taehwan MOON ,  Hagyoul BAE ,  Seunggeol NAM ,  Sangwook KIM ,  Kwanghee LEE

IPC: H01L29/86 ,  H01L27/115 ,  H01L51/05 ,  H01L27/28

Abstract: A semiconductor apparatus includes a plurality of semiconductor devices. The semiconductor devices each include a ferroelectric layer, a conductive metal oxide layer, and a semiconductor layer, between two electrodes. The conductive metal oxide layer may be between the ferroelectric layer and the semiconductor layer. The ferroelectric layer, the conductive metal oxide layer, and the semiconductor layer may all include a metal oxide. The conductive metal oxide layer may include one or more materials selected from the group consisting of an indium oxide, a zinc oxide, a tin oxide, and any combination thereof.

公开(公告)号：US20210118990A1

公开(公告)日：2021-04-22

申请号：US17072737

申请日：2020-10-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghyun JO ,  Eunha LEE ,  Jinseong HEO ,  Junghwa KIM ,  Hyangsook LEE ,  Seunggeol NAM

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L23/29

Abstract: An electronic device includes a dielectric layer including crystal grains having aligned crystal orientations the dielectric layer may be between a substrate and a gate electrode. The dielectric layer may be between isolated first and second electrodes. A method of manufacturing an electronic device may include preparing a substrate having a channel layer, forming the dielectric layer on the channel layer, and forming a gate electrode on the dielectric layer.

公开(公告)号：US20180061490A1

公开(公告)日：2018-03-01

申请号：US15448998

申请日：2017-03-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhyun LEE ,  Seunggeol NAM ,  Changhyun KIM ,  Hyeonjin SHIN ,  Yeonchoo CHO ,  Jinseong HEO ,  Seongjun PARK

IPC: G11C13/00 ,  H01L45/00 ,  H01L27/24

CPC classification number: G11C13/0004 ,  G11C13/0069 ,  G11C13/0097 ,  H01L27/24 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/141 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1641

Abstract: A phase change memory device may include a phase change layer that includes a two-dimensional (2D) material. The phase change layer may include a layered structure that includes one or more layers of 2D material. The phase change layer may be provided between a first electrode and a second electrode, and the phase of at least a portion of one or more of the layers of 2D material may be changed based on an electrical signal applied to the phase change layer through the first electrode and the second electrode. The 2D material may include a chalcogenide-based material or phosphorene. The 2D material may be associated with a phase change temperature that is greater than or equal to about 200° C. and lower than or equal to about 500° C.

公开(公告)号：US20180047818A1

公开(公告)日：2018-02-15

申请号：US15439031

申请日：2017-02-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunggeol NAM ,  Hyeonjin SHIN ,  Yeonchoo CHO ,  Minhyun LEE ,  Changhyun KIM ,  Seongjun PARK

IPC: H01L29/40 ,  H01L29/78

CPC classification number: H01L29/408 ,  H01L21/283 ,  H01L29/41725 ,  H01L29/456 ,  H01L29/66568 ,  H01L29/78 ,  H01L29/7839 ,  H01L29/786

Abstract: A semiconductor device includes a silicon semiconductor layer including at least one region doped with a first conductive type dopant, a metal material layer electrically connected to the doped region, and a self-assembled monolayer (SAM) between the doped region and the metal material layer, the SAM forming a molecular dipole on an interface of the silicon semiconductor layer in a direction of reducing a Schottky barrier height (SBH).

公开(公告)号：US20170033003A1

公开(公告)日：2017-02-02

申请号：US15172908

申请日：2016-06-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunjae SONG ,  Seunggeol NAM ,  Seongjun PARK ,  Keunwook SHIN ,  Hyeonjin SHIN ,  Jaeho LEE ,  Changseok LEE ,  Yeonchoo CHO

IPC: H01L21/768 ,  H01L21/285 ,  H01L23/532 ,  H01L29/45

CPC classification number: H01L21/76846 ,  H01L21/28525 ,  H01L21/28568 ,  H01L23/485 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53271 ,  H01L29/45

Abstract: A multilayer structure includes a first material layer, a second material layer, and a diffusion barrier layer. The second material layer is connected to the first material layer. The second material layer is spaced apart from the first material layer. The diffusion barrier layer is between the first material layer and the second material layer. The diffusion barrier layer may include a two-dimensional (2D) material. The 2D material may be a non-graphene-based material, such as a metal chalcogenide-based material having a 2D crystal structure. The first material layer may be a semiconductor or an insulator, and the second material layer may be a conductor. At least a part of the multilayer structure may constitute an interconnection for an electronic device.

Abstract translation: 多层结构包括第一材料层，第二材料层和扩散阻挡层。 第二材料层连接到第一材料层。 第二材料层与第一材料层间隔开。 扩散阻挡层在第一材料层和第二材料层之间。 扩散阻挡层可以包括二维（2D）材料。 2D材料可以是非石墨烯材料，例如具有2D晶体结构的金属硫族化物基材料。 第一材料层可以是半导体或绝缘体，第二材料层可以是导体。 多层结构的至少一部分可以构成电子设备的互连。

公开(公告)号：US20240096415A1

公开(公告)日：2024-03-21

申请号：US18335492

申请日：2023-06-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changseok LEE ,  Minhyun LEE ,  Seunggeol NAM

IPC: G11C16/04 ,  H01L29/10 ,  H01L29/18 ,  H01L29/20 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: G11C16/0483 ,  H01L29/1033 ,  H01L29/18 ,  H01L29/2003 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A nonvolatile memory device may include a channel layer extending in a first direction; a plurality of gate electrodes and a plurality of spacers alternately arranged with each other in the first direction, and a gate insulating layer extending in the first direction. Each of the plurality of gate electrodes and each of the plurality of spacers may extend in a second direction crossing the first direction. The gate insulating layer may extend in the first direction. The gate insulating layer may be between the channel layer and the plurality of gate electrodes. The channel layer may include a two-dimensional semiconductor material having an electrically p-type property.