公开(公告)号：US20250056844A1

公开(公告)日：2025-02-13

申请号：US18761631

申请日：2024-07-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunjae LEE ,  Seunggeol NAM ,  Sijung YOO ,  Dukhyun CHOE

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/51 ,  H10B51/30

Abstract: Provided is a ferroelectric field effect transistor including a source region, a drain region, a channel provided between the source region and the drain region, a ferroelectric layer provided on the channel and including a ferroelectric material including an oxide of a first element, a gate-interposed layer provided on the ferroelectric layer and including a paraelectric material including an oxide of a second element different from the first element, and a gate electrode provided on the gate-interposed layer, wherein the gate-interposed layer includes a first interposed layer adjacent to the ferroelectric layer, and a second interposed layer adjacent to the gate electrode, the first interposed layer includes a mixture of the first element and the second element, and a ratio of the first element in the first interposed layer may be greater than a ratio of the first element in the ferroelectric layer.

公开(公告)号：US20240260274A1

公开(公告)日：2024-08-01

申请号：US18414933

申请日：2024-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dukhyun CHOE ,  Jinseong HEO ,  Hyunjae LEE ,  Seunggeol NAM ,  Yoonsang PARK ,  Sijung YOO

IPC: H10B51/20 ,  H01L21/28 ,  H01L29/51 ,  H01L29/78 ,  H10B53/20

CPC classification number: H10B51/20 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/78391 ,  H10B53/20

Abstract: Provided are a memory device implementing multi-bit functionality and a memory apparatus including the memory device. The memory device includes a semiconductor substrate, a gate electrode on the semiconductor substrate, and a plurality of ferroelectric layers laminated between the semiconductor substrate and the gate electrode in a first direction perpendicular to a surface of the semiconductor substrate and including at least one first ferroelectric layer and at least one second ferroelectric layer. The first ferroelectric layer has a doping concentration gradient in which a doping concentration increases in the first direction, and the second ferroelectric layer has a doping concentration gradient in which a doping concentration decreases in the first direction. The memory device is configured to implement multi-bit functionality according to an operating voltage.

公开(公告)号：US20250126875A1

公开(公告)日：2025-04-17

申请号：US18913129

申请日：2024-10-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunjae LEE ,  Seunggeol NAM ,  Donghoon KIM ,  Sijung YOO ,  Dukhyun CHOE

IPC: H01L29/51 ,  H01L21/28 ,  H01L29/78 ,  H10B51/10 ,  H10B51/30

Abstract: Provided is a semiconductor device including a channel layer including a semiconductor material, a ferroelectric layer arranged on the channel layer and including a ferroelectric material, a gate electrode arranged on the ferroelectric layer, a first insertion layer arranged between the ferroelectric layer and the gate electrode and including a first paraelectric material, and a second insertion layer arranged between the channel layer and the ferroelectric layer and including a second paraelectric material having a dielectric constant higher than a dielectric constant of the first paraelectric material.

公开(公告)号：US20240428838A1

公开(公告)日：2024-12-26

申请号：US18748706

申请日：2024-06-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sijung YOO

IPC: G11C11/22 ,  G06N3/0464 ,  G11C7/16 ,  G11C11/54 ,  H01L29/78 ,  H10B51/30

Abstract: A synapse device including a ferroelectric field effect transistor, and a neural network apparatus including the same, are provided. The synapse device includes a first ferroelectric field effect transistor and a second ferroelectric field effect transistor electrically connected in parallel with the first ferroelectric field effect transistor, wherein the first ferroelectric field effect transistor may have a first coercive voltage, and the second ferroelectric field effect transistor may have a second coercive voltage that is greater than the first coercive voltage.

公开(公告)号：US20250126803A1

公开(公告)日：2025-04-17

申请号：US18913098

申请日：2024-10-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunggeol NAM ,  Sijung YOO ,  Minhyun LEE ,  Hyunjae LEE ,  Seokhoon CHOI

IPC: H10B51/30 ,  H10B51/20

Abstract: A semiconductor device, and a memory apparatus and an electronic apparatus including the same are provided. The semiconductor device may include a gate electrode, a ferroelectric layer on the gate electrode, a channel layer on the ferroelectric layer, and a plurality of nanostructures spaced apart from each other in the ferroelectric layer. The plurality of nanostructures may be adjacent to the gate electrode or the channel layer, or a portion of the plurality of nanostructures may be adjacent to the gate electrode and the rest portion of the plurality of nanostructures may be adjacent to the channel layer.

公开(公告)号：US20250126802A1

公开(公告)日：2025-04-17

申请号：US18761688

申请日：2024-07-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sijung YOO ,  Seunggeol NAM ,  Donghoon KIM ,  Hyunjae LEE ,  Dukhyun CHOE ,  Seokhoon CHOI

IPC: H10B51/30 ,  G06N3/063 ,  H01L29/51 ,  H01L29/78

Abstract: A ferroelectric field effect transistor includes a channel, a gate electrode provided to face the channel, a ferroelectric layer provided between the channel and the gate electrode, an interfacial layer provided between the channel and the ferroelectric layer, and a diffusion barrier layer provided between the ferroelectric layer and the gate electrode, wherein the diffusion barrier layer includes SiON, the diffusion barrier layer has an oxygen concentration gradient that gradually decreases from a first surface of the diffusion barrier layer facing the gate electrode toward a second surface of the diffusion barrier layer facing the ferroelectric layer, and the diffusion barrier layer may have a nitrogen concentration gradient that gradually increases from the first surface toward the second surface.