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公开(公告)号：US20230088827A1
公开(公告)日：2023-03-23
申请号：US17945538
申请日：2022-09-15
发明人： Seunggeol NAM , Hyunjae LEE , Dukhyun CHOE , Jinseong HEO
摘要： A semiconductor device includes: a first source/drain region; a second source/drain region; a channel between the first source/drain region and the second source/drain region; an interfacial insulating layer on the channel; a ferroelectric layer on the interfacial insulating layer; and a gate electrode on the ferroelectric layer, wherein, when a numerical value of dielectric constant of the interfacial insulating layer is K and a numerical value of remnant polarization of the ferroelectric layer is Pr, a material of the interfacial insulating layer and a material of the ferroelectric layer are selected so that K/Pr is 1 or more.
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公开(公告)号：US20220058081A1
公开(公告)日：2022-02-24
申请号：US17407028
申请日：2021-08-19
发明人： Kwonjong LEE , Sanghyo KIM , Hyojin LEE , Minyoung CHUNG , Yongsung KIL , Seungil PARK , Seunghyun LEE , Hyunjae LEE
摘要： Provided is a 5th generation (5G) or 6th generation (6G) communication system for supporting higher data rates after 4G communication systems such as long term evolution (LTE). A communication method of a user equipment (UE) includes receiving, from a base station (BS), information about a decoding mode including bit information corresponding to the number of times of perturbation, receiving data from the BS on a Physical Downlink Shared Channel (PDSCH), and decoding the received data based on the information about the decoding mode, wherein the information about the decoding mode may be generated based on service information including at least one of Quality of Service (QoS), a service priority, packet delay performance, packet error probability performance, a requirement, or a data transmission scheme.
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3.发明申请公开(公告)号：US20190055649A1
公开(公告)日：2019-02-21
申请号：US16030323
申请日：2018-07-09
发明人： Soyoung Lee , Hyunjae LEE , lk Soo KIM , Jang-Hee LEE
IPC分类号： C23C16/455 , C23C16/44 , H01L21/02
摘要： Provided are a precursor supply unit, a substrate processing system, and a method of fabricating a semiconductor device using the same. The precursor supply unit may include an outer container, an inner container provided in the outer container and used to store a precursor source, a gas injection line having an injection port, which is provided below the inner container and in the outer container and is used to provide a carrier gas into the outer container, and a gas exhaust line having an exhaust port, which is provided below the inner container and in the outer container and is used to exhaust the carrier gas in the outer container and a precursor produced from the precursor source.
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公开(公告)号：US20240015983A1
公开(公告)日：2024-01-11
申请号：US18340560
申请日：2023-06-23
发明人： Jinseong HEO , Taehwan MOON , Seunggeol NAM , Hyunjae LEE
摘要： A three-dimensional (3D) ferroelectric memory device may include a plurality of gate electrodes stacked on a substrate, a plurality of ferroelectric layers in contact with the plurality of gate electrodes, a plurality of intermediate electrodes in contact with the plurality of ferroelectric layers, a gate insulating layer in contact with the plurality of intermediate electrodes, and a channel layer in contact with the gate insulating layer. Widths of the intermediate electrodes may be greater than widths of the ferroelectric layers in contact with the intermediate electrodes.
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公开(公告)号：US20240008289A1
公开(公告)日：2024-01-04
申请号：US18340407
申请日：2023-06-23
发明人： Jinseong HEO , Taehwan MOON , Seunggeol NAM , Hyunjae LEE
摘要： Provided is a 3D ferroelectric memory device. The 3D ferroelectric memory device may include a plurality of gate electrodes stacked on a substrate in a first direction; a plurality of ferroelectric layers on the plurality of gate electrodes in a second direction; a plurality of intermediate electrodes on the plurality of ferroelectric layers in the second direction; a first insulating layer between the plurality of gate electrodes and between the plurality of intermediate electrodes; a second insulating layer on the plurality of intermediate electrodes and the first insulating layer; and a channel layer on the second insulating layer.
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公开(公告)号：US20230397432A1
公开(公告)日：2023-12-07
申请号：US18329197
申请日：2023-06-05
发明人： Jinseong HEO , Taehwan MOON , Seunggeol NAM , Hyunjae LEE , Dukhyun CHOE
CPC分类号： H10B53/20 , H10B53/10 , G11C16/0483 , H10B51/10 , H10B51/20
摘要： A memory device includes a plurality of gate electrodes spaced apart from each other in a first direction, a memory layer comprising a plurality of memory regions that protrude and extend in a second direction perpendicular to the first direction to face the plurality of gate electrodes, respectively, a plurality of first insulating layers extended to spaces between the plurality of memory regions between the plurality of gate electrodes, a channel layer disposed between the memory layer and the plurality of gate electrodes, the channel layer having a shape including a plurality of first regions surrounding the plurality of memory regions and a second region that connects the plurality of first regions to each other in the first direction, and a gate insulating layer arranged between the channel layer and the plurality of gate electrodes.
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公开(公告)号：US20240172447A1
公开(公告)日：2024-05-23
申请号：US18491161
申请日：2023-10-20
发明人： Seunggeol NAM , Jinseong HEO , Hyunjae LEE , Dukhyun CHOE
CPC分类号： H10B51/20 , H01L29/40111 , H01L29/516 , H01L29/78391 , H10B51/10
摘要： Provided is a three-dimensional (3D) ferroelectric memory device. The 3D ferroelectric memory device includes a substrate, a plurality of insulating layers stacked on the substrate, a plurality of gate electrodes between the plurality of insulating layers, a plurality of gate insulating layers in contact with the plurality of gate electrodes, a plurality of intermediate electrodes in contact with the plurality of gate insulating layers, a ferroelectric layer in contact with the plurality of intermediate electrodes and the plurality of insulating layers, and a channel layer in contact with the ferroelectric layer.
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8.发明公开公开(公告)号：US20230275150A1
公开(公告)日：2023-08-31
申请号：US18168699
申请日：2023-02-14
发明人： Hyunjae LEE , Jinseong HEO , Seunggeol NAM , Taehwan MOON , Hagyoul BAE
CPC分类号： H01L29/78391 , H01L29/7606
摘要： A semiconductor device may include a semiconductor substrate including a dopant having a polarity; a channel layer on the semiconductor substrate and including majority carriers having a polarity opposite to a polarity of the semiconductor substrate; a ferroelectric layer on the channel layer; and a gate on the ferroelectric layer. A doping concentration of the semiconductor substrate may be less than a concentration of the majority carrier of the channel layer.
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公开(公告)号：US20240244848A1
公开(公告)日：2024-07-18
申请号：US18412793
申请日：2024-01-15
发明人： Hyunjae LEE , Jinseong HEO , Seunggeol NAM , Yunseong LEE , Dukhyun CHOE
摘要： Provided is a semiconductor device including a ferroelectric layer. The semiconductor device includes a channel layer including an n-type oxide semiconductor layer and a p-type oxide semiconductor layer, a ferroelectric layer disposed on the channel layer, a gate electrode disposed on the ferroelectric layer, and a reduced layer disposed on the channel layer and including an element having greater reducing power than a metal included in the channel layer.
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10.发明公开公开(公告)号：US20240162346A1
公开(公告)日：2024-05-16
申请号：US18495220
申请日：2023-10-26
发明人： Sanghyun JO , Jinseong HEO , Kihong KIM , Hyunjae LEE
CPC分类号： H01L29/78391 , H01L28/60 , H01L29/516 , H01L29/6684 , H10B12/31
摘要： A field effect transistor includes a source region, a drain region, a channel between the source region and the drain region, a gate insulating layer configured to cover an upper surface of the channel, and a gate electrode configured to cover an upper surface of the gate insulating layer. The gate insulating layer includes a first region where a ferroelectric crystal structure is dominant and a second region where a non-ferroelectric structure is dominant. The gate electrode includes a first pattern region facing the first region of the gate insulating layer and a second pattern region facing the second region of the gate insulating layer.
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