公开(公告)号：US20230065578A1

公开(公告)日：2023-03-02

申请号：US17847744

申请日：2022-06-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngjun HWANG ,  Hongrak SON ,  Geunyeong YU

IPC: G11C29/52 ,  G11C29/02 ,  G11C7/10 ,  G11C7/22

Abstract: Various example embodiments of the inventive concepts provide an error correction circuit and a semiconductor device. The error correction circuit includes clock-sync distributor circuitry configured to output a plurality of distributor output data based on distributor reception data received using a first clock signal, each of the plurality of distributor output data output based on the first clock signal or a second clock signal, the second clock signal having a higher frequency than a frequency of the first clock signal, a node processor configured to generate a plurality of output data by performing error correction decoding using the plurality of distributor output data, output a first subset of the plurality of output data based on the first clock signal, and output a second subset of the plurality of output data based on the second clock signal, and clock-sync combiner circuitry configured to output, based on the first clock signal, the plurality of output data received from the node processor.

公开(公告)号：US20240120945A1

公开(公告)日：2024-04-11

申请号：US18225313

申请日：2023-07-24

Applicant: SAMSUNG ELECTRONICS CO, LTD.

Inventor： Daeyeol YANG ,  Bohwan JUN ,  Hongrak SON ,  Geunyeong YU ,  Youngjun HWANG

IPC: H03M13/11

CPC classification number: H03M13/116 ,  H03M13/1108 ,  H03M13/1177

Abstract: A generalized low-density parity-check (G-LDPC) encoder, including a plurality of generalized constraint (GC) encoders configured to perform a plurality of GC encoding operations in parallel based on a GC code having a quasi-cyclic (QC) structure including information variable nodes, inner parity variable nodes, and super check nodes configured to perform multiple condition checks, wherein each GC encoder of the plurality of GC encoders includes a plurality of first logic circuits configured to perform a GC encoding operation of the plurality of GC encoding operations; and an LDPC encoder configured to perform an LDPC encoding operation based on an LDPC code having the QC structure, wherein the LDPC encoder includes a plurality of single check nodes configured to perform a single parity check, wherein the each GC encoder is configured to receive information bits, and to determine parity bits of a portion of inner parity bits corresponding to the information bits by enabling only a portion of the plurality of first logic circuits to perform the GC encoding operation, and wherein the LDPC encoder is configured to: obtain the inner parity bits by combining the parity bits obtained from the plurality of GC encoders, determine outer parity bits corresponding to the information bits and the inner parity bits by performing the LDPC encoding operation, and output the information bits, the inner parity bits, and the outer parity bits as a codeword.

公开(公告)号：US20250060885A1

公开(公告)日：2025-02-20

申请号：US18421352

申请日：2024-01-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woohyun KANG ,  Garam KIM ,  Jisoo KIM ,  Sangkwon MOON ,  Hyunkyo HO ,  Jin Gu JEONG ,  Youngjun HWANG

IPC: G06F3/06

Abstract: A storage device according to an embodiment includes a memory device configured to apply a first program voltage and a first verification voltage to a first word line and output, based on a program state of each of a plurality of memory cells connected to the first word line, a speed information representing a speed characteristic of each of the plurality of memory cells; and a memory controller configured to determine at least one memory cell to be programmed into a predetermined program state; determine, among the at least one memory cell, at least one target memory cell having a first speed characteristic based on the speed information; and perform a state-shaping operation to convert a data corresponding to the predetermined program state for the at least one target memory cell into a value corresponding to a program state different from the predetermined program state.

公开(公告)号：US20240340025A1

公开(公告)日：2024-10-10

申请号：US18520707

申请日：2023-11-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kijun JEON ,  Kyoungbin PARK ,  Hong Rak SON ,  Dae-Yeol YANG ,  Geunyeong YU ,  Bohwan JUN ,  Youngjun HWANG

IPC: H03M13/11 ,  H03M13/00

CPC classification number: H03M13/1168 ,  H03M13/616

Abstract: A semiconductor device may include an error correcting code (ECC) encoder that encodes a codeword based on a parity check matrix and generates the encoded codeword including an information bit and a parity bit. The parity check matrix is divided into an information part corresponding to the information bit and a parity part corresponding to the parity bit. The parity part includes a block matrix T including a plurality of first sub-matrices arranged in a dual diagonal structure, a block matrix B including a first sub-matrix and a (1−a)-th sub-matrix, a block matrix D composed of a first sub-matrix, and a block matrix E including a first sub-matrix and a masked (1−(a+1))-th sub-matrix. A location where the first sub-matrix is placed in the block matrix B precedes a location where the masked (1−(a+1))-th sub-matrix is placed in the block matrix E.

公开(公告)号：US20220130485A1

公开(公告)日：2022-04-28

申请号：US17244195

申请日：2021-04-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngjun HWANG ,  Heeyoul KWAK ,  Bohwan JUN ,  Hongrak SON ,  Dongmin SHIN ,  Geunyeong YU

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/00 ,  G11C16/10 ,  G11C16/26

Abstract: A memory device includes a cell array including a plurality of pages and a control logic configured to control program and read operations of the cell array. The control logic controls the program and read operations to store first through N-th codewords in a first page among the pages and program a page parity corresponding in common to the first through N-th codewords to the first page in response to a program command for a page unit and to selectively read the first codeword among the first through N-th codewords in response to a read command for a sub-page unit, where N is an integer of at least 2. The first codeword includes first sub-page data and a first sub-parity corresponding thereto, and the first sub-parity includes information for correcting an error in the first sub-page data through error correction code (ECC) decoding independently performed on each codeword.

公开(公告)号：US20210397514A1

公开(公告)日：2021-12-23

申请号：US17134961

申请日：2020-12-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngjun HWANG ,  Hongrak SON ,  Dongmin SHIN

IPC: G06F11/10 ,  H03M13/11 ,  H03M13/45

Abstract: An error check code (ECC) decoder includes a buffer, a data converter and a decoding circuit. The buffer stores a plurality of read pages read from a plurality of multi-level cells connected to a same wordline. The data converter adjusts reliability parameters of read bits of the plurality of read pages based on state-bit mapping information and the plurality of read pages to generate a plurality of ECC input data respectively corresponding to the plurality of read pages. The state-bit mapping information indicate mapping relationships between states and bits stored in the plurality of multi-level cells. The decoding circuit performs an ECC decoding operation with respect to the plurality of read pages based on the plurality of ECC input data. An error correction probability is increased by adjusting the reliability parameters of read bits based on the state-bit mapping information.