公开(公告)号：US10825526B1

公开(公告)日：2020-11-03

申请号：US16450042

申请日：2019-06-24

Applicant: SanDisk Technologies LLC

Inventor： YenLung Li ,  Hua-Ling Cynthia Hsu ,  Chen Chen ,  Min Peng

IPC: G11C16/26 ,  G11C16/10 ,  G11C16/04 ,  G11C11/56

Abstract: In non-volatile memory circuit, the area devoted to the cache buffer of the read and write circuitry is reduced through the sharing of data latches. In an array structure where memory cells are connected along bit lines, and the bit lines organized into columns, each of the columns has an associated set of data latches, including one or more data latches for each bit line of the column. Data is transferred in and out of the read and write circuit on a data bus, where data is transferred between the data latches and the data bus through a set of transfers latches. The area used by the latch structure is reduced by sharing the transfer latches of the read and write circuitry between the data latches of multiple columns.

公开(公告)号：US10811082B1

公开(公告)日：2020-10-20

申请号：US16450058

申请日：2019-06-24

Applicant: SanDisk Technologies LLC

Inventor： YenLung Li ,  Hua-Ling Cynthia Hsu ,  Chen Chen ,  Min Peng

IPC: G11C7/18 ,  G11C11/409 ,  G06F3/06

Abstract: In a non-volatile memory circuit, read and write performance is improved by increasing the transfer rate of data through the cache buffer during read and write operations. In an array structure where memory cells are connected along bit lines, and the bit lines organized into columns, pairs of data words are stored interleaved on the bit lines of a pair of columns. Data is transferred in and out of the read and write circuit on an internal bus structure, where part of the transfer of one word stored on a pair of columns can overlap with part of the transfer of another word, accelerating transfer times for both read and write.

公开(公告)号：US11386961B2

公开(公告)日：2022-07-12

申请号：US16722538

申请日：2019-12-20

Applicant: SanDisk Technologies LLC

Inventor： YenLung Li ,  Chen Chen ,  Min Peng ,  Mitsuyuki Watanabe

IPC: G06F3/00 ,  G11C16/10 ,  G06F13/16 ,  G11C16/26 ,  G11C16/04 ,  H03M9/00

Abstract: In a non-volatile memory circuit, performance is improved by converting data between a serial format, for transfer on and off of the memory circuit, and a parallel format, for transfer to and from the memory latches used for read and writing data into the memory array of the memory circuit. The memory array is split into M+N divisions, but transferred with a degree of parallelism of M, allowing M words of data to be transferred in parallel at a fixed transfer rate while allowing for up to N bad columns in a transfer. In the write path, a column skipping mechanism is used when converting words of write data into a parallel format. In the read path, a set of (M+N) to 1 multiplexers is used to align the word of read data so that read data can be transferred at a fixed rate and without any added latency.

公开(公告)号：US20210193226A1

公开(公告)日：2021-06-24

申请号：US16722538

申请日：2019-12-20

Applicant: SanDisk Technologies LLC

Inventor： YenLung Li ,  Chen Chen ,  Min Peng ,  Mitsuyuki Watanabe

IPC: G11C16/10 ,  G06F13/16 ,  H03M9/00 ,  G11C16/04 ,  G11C16/26

Abstract: In a non-volatile memory circuit, performance is improved by converting data between a serial format, for transfer on and off of the memory circuit, and a parallel format, for transfer to and from the memory latches used for read and writing data into the memory array of the memory circuit. The memory array is split into M+N divisions, but transferred with a degree of parallelism of M, allowing M words of data to be transferred in parallel at a fixed transfer rate while allowing for up to N bad columns in a transfer. In the write path, a column skipping mechanism is used when converting words of write data into a parallel format. In the read path, a set of (M+N) to 1 multiplexers is used to align the word of read data so that read data can be transferred at a fixed rate and without any added latency.

公开(公告)号：US10726940B2

公开(公告)日：2020-07-28

申请号：US16239517

申请日：2019-01-03

Applicant: SanDisk Technologies LLC

Inventor： Zhuojie Li ,  Hua-Ling Cynthia Hsu ,  Yen-Lung Li ,  Min Peng

IPC: G11C29/00 ,  G11C16/10 ,  G06F11/10

Abstract: Apparatuses, systems, and methods are disclosed for skip inconsistency correction. A skip circuit is configured to skip memory units for read operations and write operations of a memory array, based on a record of memory units identified as faulty. A skip inconsistency detection circuit is configured to detect a skip inconsistency in read data from a memory array. A correction circuit is configured to correct a skip inconsistency and output corrected read data.

公开(公告)号：US10971202B1

公开(公告)日：2021-04-06

申请号：US16849827

申请日：2020-04-15

Applicant: SanDisk Technologies LLC

Inventor： Chen Chen ,  Yenlung Li ,  Min Peng

IPC: G11C16/26 ,  G11C7/22 ,  G11C7/10

Abstract: Apparatuses and techniques are described for transferring data out of a memory device with low latency. Data can be stored in data transfer latches for NAND strings arranged in columns in divisions of a block. Data can be output from the data transfer latches for different columns in different divisions in each transfer. For example, the data output can include data from an nth column in some divisions and an n+1st column in other divisions. This avoids outputting unwanted data at the start of a data transfer. The data from the data transfer latches is output to a data pipeline and then to a set of control latch circuits. The data can be clocked out from a last control latch circuit of the set in a desired division order by use of separate multiplexer control signals for the control latch circuits.