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1.发明申请公开(公告)号：US20190066789A1
公开(公告)日：2019-02-28
申请号：US15844037
申请日：2017-12-15
发明人： Manabu Sakai , Qui Vi Nguyen , Yen-Lung Li
摘要： This disclosure provides techniques for reducing leakage current in a non-volatile memory that does not include a local interconnect. In one example, a low-voltage pulse can be applied to all of the word-lines in all of the blocks of the non-volatile memory. The low-voltage pulse can be applied during a period in which the row decoder is typically idle in order to reduce the total amount of time required to program the non-volatile memory. After the conclusion low-voltage pulse, a global control line voltage can be applied at about the same level as the low-voltage pulse to keep the word-lines floating when the pulse is no longer applied.
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公开(公告)号：US20210383879A1
公开(公告)日：2021-12-09
申请号：US16893859
申请日：2020-06-05
发明人： Lei Lin , Wei Zhao , Henry Chin , Yen-Lung Li
摘要： A memory apparatus and method of operation is provided. The apparatus includes selected memory cells coupled to a selected word line and each storing a threshold voltage representative of a selected cell data programmed in a program-verify operation. Unselected memory cells are coupled to a neighbor word line disposed adjacent the selected word line. A control circuit is coupled to the selected and unselected memory cells and configured to ramp from at least one initial voltage applied to the neighbor word line directly to a target neighbor verify voltage without exceeding or falling below the target neighbor verify voltage thereby assisting the selected word line reach at least one verify reference voltage used in verifying the threshold voltage of the selected memory cells during at least one verify stage of the program-verify operation following a program operation of the program-verify operation.
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公开(公告)号：US10908838B2
公开(公告)日：2021-02-02
申请号：US16354004
申请日：2019-03-14
发明人： Dike Zhou , Yen-Lung Li
IPC分类号： G06F3/06
摘要： Apparatuses, systems, and methods are presented for column replacement. An input register, which includes a set of input divisions, may receive write data for a memory array. An output register, which includes a set of normal output divisions and a set of replacement output divisions, may output write data to an array. A column replacement circuit may selectively couple input divisions to output divisions. A column replacement circuit may couple normal output divisions for functional columns of an array to corresponding input divisions. A column replacement circuit may couple replacement output divisions for functional columns of an array to input divisions selected by the column replacement circuit, which may be corresponding input divisions or other input divisions.
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公开(公告)号：US10475493B2
公开(公告)日：2019-11-12
申请号：US15844037
申请日：2017-12-15
发明人： Manabu Sakai , Qui Vi Nguyen , Yen-Lung Li
摘要： This disclosure provides techniques for reducing leakage current in a non-volatile memory that does not include a local interconnect. In one example, a low-voltage pulse can be applied to all of the word-lines in all of the blocks of the non-volatile memory. The low-voltage pulse can be applied during a period in which the row decoder is typically idle in order to reduce the total amount of time required to program the non-volatile memory. After the conclusion low-voltage pulse, a global control line voltage can be applied at about the same level as the low-voltage pulse to keep the word-lines floating when the pulse is no longer applied.
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公开(公告)号：US10726940B2
公开(公告)日：2020-07-28
申请号：US16239517
申请日：2019-01-03
发明人： Zhuojie Li , Hua-Ling Cynthia Hsu , Yen-Lung Li , Min Peng
摘要： Apparatuses, systems, and methods are disclosed for skip inconsistency correction. A skip circuit is configured to skip memory units for read operations and write operations of a memory array, based on a record of memory units identified as faulty. A skip inconsistency detection circuit is configured to detect a skip inconsistency in read data from a memory array. A correction circuit is configured to correct a skip inconsistency and output corrected read data.
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公开(公告)号：US10153051B1
公开(公告)日：2018-12-11
申请号：US15879044
申请日：2018-01-24
发明人： Hong-Yan Chen , Yingda Dong , Yen-Lung Li
摘要： A memory device and associated techniques for programming a select gate transistor. The programming of the select gate transistors in a NAND string is performed under similar biasing as is seen during the programming of a memory cell, when the select gate transistors are required to be in the conductive or non-conductive state for selected and unselected NAND strings, respectively. Program-verify tests for the select gate transistors use a current which flows from the source end to the drain end of the NAND string, and can be performed separately for odd- and even-numbered NAND strings, to avoid the effects of bit line-to-bit line coupling. The tests account for uneven doping in the channel of the select gate transistor. Program-verify tests for the memory cells use a current which flows from the drain end to the source end and can be performed concurrently.
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