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    Dynamic word line reconfiguration for NAND structure
    1.
    发明授权
    Dynamic word line reconfiguration for NAND structure 有权

    公开(公告)号：US11990185B2

    公开(公告)日：2024-05-21

    申请号：US17888063

    申请日：2022-08-15

    Applicant: SanDisk Technologies LLC

    Inventor： Xiang Yang ,  YenLung Li ,  James Kai

    IPC: G11C16/08 ,  G11C16/04 ,  G11C16/10 ,  G11C16/16

    CPC classification number: G11C16/08 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16

    Abstract: Technology is disclosed herein reconfiguring word lines as either data word lines or dummy word lines. In a sub-block mode reconfigurable word lines are used as dummy word lines that provide electrical isolation between data word lines in a block. The block may be divided into an upper tier, a middle tier, and a lower tier, with the reconfigurable word lines within the middle tier. In a full-block mode the reconfigurable group of the word lines are used as data word lines. Because the reconfigurable word lines are used as data word lines in the full-block mode storage capacity is greater in the full-block mode than in the sub-block mode. Moreover, because the sub-blocks are smaller in size but greater in number than the full-blocks, the memory system may be provisioned with fewer blocks and still meet user storage requirements in both the full-block mode and the sub-block mode.

    Non-volatile memory with reduced data cache buffer
    2.
    发明授权
    Non-volatile memory with reduced data cache buffer 有权

    公开(公告)号：US10825526B1

    公开(公告)日：2020-11-03

    申请号：US16450042

    申请日：2019-06-24

    Applicant: SanDisk Technologies LLC

    Inventor： YenLung Li ,  Hua-Ling Cynthia Hsu ,  Chen Chen ,  Min Peng

    IPC: G11C16/26 ,  G11C16/10 ,  G11C16/04 ,  G11C11/56

    Abstract: In non-volatile memory circuit, the area devoted to the cache buffer of the read and write circuitry is reduced through the sharing of data latches. In an array structure where memory cells are connected along bit lines, and the bit lines organized into columns, each of the columns has an associated set of data latches, including one or more data latches for each bit line of the column. Data is transferred in and out of the read and write circuit on a data bus, where data is transferred between the data latches and the data bus through a set of transfers latches. The area used by the latch structure is reduced by sharing the transfer latches of the read and write circuitry between the data latches of multiple columns.

    Non-volatile memory with fast data cache transfer scheme
    3.
    发明授权
    Non-volatile memory with fast data cache transfer scheme 有权

    公开(公告)号：US10811082B1

    公开(公告)日：2020-10-20

    申请号：US16450058

    申请日：2019-06-24

    Applicant: SanDisk Technologies LLC

    Inventor： YenLung Li ,  Hua-Ling Cynthia Hsu ,  Chen Chen ,  Min Peng

    IPC: G11C7/18 ,  G11C11/409 ,  G06F3/06

    Abstract: In a non-volatile memory circuit, read and write performance is improved by increasing the transfer rate of data through the cache buffer during read and write operations. In an array structure where memory cells are connected along bit lines, and the bit lines organized into columns, pairs of data words are stored interleaved on the bit lines of a pair of columns. Data is transferred in and out of the read and write circuit on an internal bus structure, where part of the transfer of one word stored on a pair of columns can overlap with part of the transfer of another word, accelerating transfer times for both read and write.

    Centralized variable rate serializer and deserializer for bad column management
    4.
    发明授权
    Centralized variable rate serializer and deserializer for bad column management 有权
    集中可变速率序列化器和解串器，用于色谱柱管理不良

    公开(公告)号：US09490035B2

    公开(公告)日：2016-11-08

    申请号：US14104817

    申请日：2013-12-12

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Wanfang Tsai ,  YenLung Li ,  Chen Chen

    IPC: G11C7/00 ,  G11C29/00

    CPC classification number: G11C29/82 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3404 ,  G11C29/808 ,  G11C2207/107

    Abstract: A memory circuit includes an array subdivided into multiple divisions, each connectable to a corresponding set of access circuitry. A serializer/deserializer circuit is connected to a data bus and the access circuitry to convert data between a (word-wise) serial format on the bus and (multi-word) parallel format for the access circuitry. Column redundancy circuitry is connect to the serializer/deserializer circuit to provide defective column information about the array. In converting data from a serial to a parallel format, the serializer/deserializer circuit skips words of the data in the parallel format based on the defective column information indicating that the location corresponds to a defective column. In converting data from a parallel to a serial format the serializer/deserializer circuit skips words of the data in the parallel format based on the defective column information indicating that the location corresponds to a defective column.

    Abstract translation: 存储器电路包括细分成多个分区的阵列，每个分区可连接到对应的一组接入电路。 串行器/解串器电路连接到数据总线和访问电路，用于在总线上的（逐字）串行格式和用于访问电路的（多字）并行格式之间转换数据。 列冗余电路连接到串行器/解串器电路，以提供关于阵列的有缺陷的列信息。 在将数据从串行格式转换为并行格式时，串行器/解串器电路基于指示位置对应于缺陷列的缺陷列信息，以并行格式跳过数据字。 在将数据从并行转换为串行格式时，串行器/解串器电路基于指示该位置对应于缺陷列的缺陷列信息，以并行格式跳过数据字。

    USE OF DATA LATCHES FOR COMPRESSION OF SOFT BIT DATA IN NON-VOLATILE MEMORIES
    6.
    发明申请
    USE OF DATA LATCHES FOR COMPRESSION OF SOFT BIT DATA IN NON-VOLATILE MEMORIES 有权

    公开(公告)号：US20230081623A1

    公开(公告)日：2023-03-16

    申请号：US17666657

    申请日：2022-02-08

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Hua-Ling Cynthia Hsu ,  Masaaki Higashitani ,  YenLung Li ,  Chen Chen

    IPC: G11C16/26 ,  G11C16/24 ,  G11C16/04 ,  H03M13/11 ,  H03M13/00

    Abstract: For a non-volatile memory that uses hard bit and soft bit data in error correction operations, to reduce the amount of soft bit data that needs to be transferred from a memory to the controller and improve memory system performance, the soft bit data can be compressed before transfer. After the soft bit data is read and stored into the internal data latches associated with the sense amplifiers, it is compressed within these internal data latches. The compressed soft bit data can then be transferred to the transfer data latches of a cache buffer, where the compressed soft bit data can be consolidated and transferred out over an input-output interface. Within the input-output interface, the compressed data can be reshuffled to put into logical user data order if needed.

    ARCHITECTURE AND DATA PATH OPTIONS FOR COMPRESSION OF SOFT BIT DATA IN NON-VOLATILE MEMORIES
    7.
    发明申请
    ARCHITECTURE AND DATA PATH OPTIONS FOR COMPRESSION OF SOFT BIT DATA IN NON-VOLATILE MEMORIES 有权

    公开(公告)号：US20230080999A1

    公开(公告)日：2023-03-16

    申请号：US17557433

    申请日：2021-12-21

    Applicant: SanDisk Technologies LLC

    Inventor： Hua-Ling Cynthia Hsu ,  A. Harihara Sravan ,  YenLung Li

    IPC: G06F12/0893 ,  G11C16/26

    Abstract: For a non-volatile memory that uses hard bit and a soft bit data in error correction operations, architectures are introduced for the compression of the soft bit data to reduce the amount of data transferred over the memory's input-output interface. For a memory device with multiple planes of memory cells, the internal global data bus is segmented and a data compression circuit associated with each segment. This allows soft bit data from a cache buffer of a plane using one segment to transfer data between the cache buffer and the associated compression circuit concurrently with transferring data from a cache buffer of another plane using another segment, either for compression or transfer to the input-output interface.

    NON-VOLATILE STORAGE SYSTEM WITH POWER ON READ TIMING REDUCTION
    10.
    发明公开
    NON-VOLATILE STORAGE SYSTEM WITH POWER ON READ TIMING REDUCTION 审中-公开

    公开(公告)号：US20230260589A1

    公开(公告)日：2023-08-17

    申请号：US17672904

    申请日：2022-02-16

    Applicant: SanDisk Technologies LLC

    Inventor： Hua-Ling Cynthia Hsu ,  YenLung Li

    IPC: G11C29/50

    CPC classification number: G11C29/50004 ,  G11C2029/5004

    Abstract: Technology is disclosed herein for loading redundancy information during a memory system power on read (POR). A memory structure has primary regions (e.g., primary columns) and a number of redundant regions (e.g., redundant columns). The status of the regions is stored in isolation latches during the POR. Initially, simultaneously all latches for primary regions are reset to used and all latches for redundant regions are reset to unused. Then, isolation latches for defective primary regions are set to unused while isolation latches for corresponding redundant regions are set to used. There is no need to individually set isolation latches for redundant regions to unused, which saves time during POR. Moreover, whenever the isolation latch for a defective primary region is set from used to unused, in parallel the isolation latch for the replacement redundant column may be set from unused to used, thereby not incurring a time penalty.

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