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    Apparatus for controlling rounding modes in single instruction multiple data (SIMD) floating-point units
    3.
    发明授权
    Apparatus for controlling rounding modes in single instruction multiple data (SIMD) floating-point units 失效
    用于在单指令多数据（SIMD）浮点单元中控制舍入模式的装置

    公开(公告)号：US07447725B2

    公开(公告)日：2008-11-04

    申请号：US10982110

    申请日：2004-11-05

    申请人： Sang Hoo Dhong ,  Harm Peter Hofstee ,  Christian Jacobi ,  Silvia Melitta Mueller ,  Hwa-Joon Oh

    发明人： Sang Hoo Dhong ,  Harm Peter Hofstee ,  Christian Jacobi ,  Silvia Melitta Mueller ,  Hwa-Joon Oh

    IPC分类号： G06F7/38

    CPC分类号： G06F7/49947 ,  G06F7/483 ,  G06F7/49968 ,  G06F7/49973 ,  G06F7/49989 ,  G06F2207/3828

    摘要： An apparatus for controlling rounding modes in a single instruction multiple data (SIMD) floating-point unit is disclosed. The SIMD floating-point unit includes a floating-point status-and-control register (FPSCR) having a first rounding mode bit field and a second rounding mode bit field. The SIMD floating-point unit also includes means for generating a first slice and a second slice. During a floating-point operation, the SIMD floating-point unit concurrently performs a first rounding operation on the first slice and a second rounding operation on the second slice according to a bit in the first rounding mode bit field and a bit in the second rounding mode bit field within the FPSCR, respectively.

    摘要翻译： 公开了一种用于在单指令多数据（SIMD）浮点单元中控制舍入模式的装置。 SIMD浮点单元包括具有第一舍入模式位字段和第二舍入模式位字段的浮点状态和控制寄存器（FPSCR）。 SIMD浮点单元还包括用于生成第一切片和第二切片的装置。 在浮点运算期间，SIMD浮点单元根据第一舍入模式位字段中的位并且在第二舍入中的位同时对第一切片进行第一舍入运算，并对第二切片进行第二舍入运算 FPSCR中的模式位字段。

    Method for controlling rounding modes in single instruction multiple data (SIMD) floating-point units
    4.
    发明授权
    Method for controlling rounding modes in single instruction multiple data (SIMD) floating-point units 有权
    用于控制单指令多数据（SIMD）浮点单元中舍入模式的方法

    公开(公告)号：US08229989B2

    公开(公告)日：2012-07-24

    申请号：US12238500

    申请日：2008-09-26

    申请人： Sang Hoo Dhong ,  Harm Peter Hofstee ,  Christian Jacobi ,  Silvia Melitta Mueller ,  Hwa-Joon Oh

    发明人： Sang Hoo Dhong ,  Harm Peter Hofstee ,  Christian Jacobi ,  Silvia Melitta Mueller ,  Hwa-Joon Oh

    IPC分类号： G06F7/38

    CPC分类号： G06F7/49947 ,  G06F7/483 ,  G06F7/49968 ,  G06F7/49973 ,  G06F7/49989 ,  G06F2207/3828

    摘要： A method for controlling rounding modes in a single instruction multiple data (SIMD) floating-point unit is disclosed. The SIMD floating-point unit includes a floating-point status-and-control register (FPSCR) having a first rounding mode bit field and a second rounding mode bit field. The SIMD floating-point unit also includes means for generating a first slice and a second slice. During a floating-point operation, the SIMD floating-point unit concurrently performs a first rounding operation on the first slice and a second rounding operation on the second slice according to a bit in the first rounding mode bit field and a bit in the second rounding mode bit field within the FPSCR, respectively.

    摘要翻译： 公开了一种用于在单指令多数据（SIMD）浮点单元中控制舍入模式的方法。 SIMD浮点单元包括具有第一舍入模式位字段和第二舍入模式位字段的浮点状态和控制寄存器（FPSCR）。 SIMD浮点单元还包括用于生成第一切片和第二切片的装置。 在浮点运算期间，SIMD浮点单元根据第一舍入模式位字段中的位并且在第二舍入中的位同时对第一切片进行第一舍入运算，并对第二切片进行第二舍入运算 FPSCR中的模式位字段。

    Method for Controlling Rounding Modes in Single Instruction Multiple Data (SIMD) Floating-Point Units
    5.
    发明申请
    Method for Controlling Rounding Modes in Single Instruction Multiple Data (SIMD) Floating-Point Units 有权
    用于控制单指令多数据（SIMD）浮点单元中舍入模式的方法

    公开(公告)号：US20090024684A1

    公开(公告)日：2009-01-22

    申请号：US12238500

    申请日：2008-09-26

    申请人： Sang Hoo Dhong ,  Harm Peter Hofstee ,  Christian Jacobi ,  Silvia Melitta Mueller ,  Hwa-Joon Oh

    发明人： Sang Hoo Dhong ,  Harm Peter Hofstee ,  Christian Jacobi ,  Silvia Melitta Mueller ,  Hwa-Joon Oh

    IPC分类号： G06F7/483

    CPC分类号： G06F7/49947 ,  G06F7/483 ,  G06F7/49968 ,  G06F7/49973 ,  G06F7/49989 ,  G06F2207/3828

    摘要： A method for controlling rounding modes in a single instruction multiple data (SIMD) floating-point unit is disclosed. The SIMD floating-point unit includes a floating-point status-and-control register (FPSCR) having a first rounding mode bit field and a second rounding mode bit field. The SIMD floating-point unit also includes means for generating a first slice and a second slice. During a floating-point operation, the SIMD floating-point unit concurrently performs a first rounding operation on the first slice and a second rounding operation on the second slice according to a bit in the first rounding mode bit field and a bit in the second rounding mode bit field within the FPSCR, respectively.

    摘要翻译： 公开了一种用于在单指令多数据（SIMD）浮点单元中控制舍入模式的方法。 SIMD浮点单元包括具有第一舍入模式位字段和第二舍入模式位字段的浮点状态和控制寄存器（FPSCR）。 SIMD浮点单元还包括用于生成第一切片和第二切片的装置。 在浮点运算期间，SIMD浮点单元根据第一舍入模式位字段中的位并且在第二舍入中的位同时对第一切片进行第一舍入运算，并对第二切片进行第二舍入运算 FPSCR中的模式位字段。

    Byte execution unit for carrying out byte instructions in a processor
    6.
    发明授权
    Byte execution unit for carrying out byte instructions in a processor 失效
    用于在处理器中执行字节指令的字节执行单元

    公开(公告)号：US07149877B2

    公开(公告)日：2006-12-12

    申请号：US10621908

    申请日：2003-07-17

    申请人： Sang Hoo Dhong ,  Hwa-Joon Oh ,  Brad William Michael ,  Silvia Melitta Mueller ,  Kevin D. Tran

    发明人： Sang Hoo Dhong ,  Hwa-Joon Oh ,  Brad William Michael ,  Silvia Melitta Mueller ,  Kevin D. Tran

    IPC分类号： G06F15/76

    CPC分类号： G06F9/30014 ,  G06F9/30036

    摘要： A disclosed byte execution unit receives byte instruction information and two operands, and performs an operation specified by the byte instruction information upon one or both of the operands, thereby producing a result. The byte instruction specifies either a count ones in bytes operation, an average bytes operation, an absolute differences of bytes operation, or a sum bytes into halfwords operation. In one embodiment, the byte execution unit includes multiple byte units. Each byte unit includes multiple population counters, two compressor units, adder input multiplexer logic, adder logic, and result multiplexer logic. A data processing system is described including a processor coupled to a memory system. The processor includes the byte execution unit. The memory system includes a byte instruction, wherein the byte instruction specifies either the count ones in bytes operation, the average bytes operation, the absolute differences of bytes operation, or the sum bytes into halfwords operation.

    摘要翻译： 公开的字节执行单元接收字节指令信息和两个操作数，并且在一个或两个操作数上执行由字节指令信息指定的操作，从而产生结果。 字节指令指定以字节为单位的计数值，平均字节操作，字节操作的绝对差值，或字节字节到半字操作。 在一个实施例中，字节执行单元包括多个字节单元。 每个字节单元包括多个总体计数器，两个压缩器单元，加法器输入复用器逻辑，加法器逻辑和结果复用器逻辑。 描述了包括耦合到存储器系统的处理器的数据处理系统。 处理器包括字节执行单元。 存储器系统包括一个字节指令，其中字节指令指定字节操作中的计数值，平均字节操作，字节操作的绝对差值，或字节数字到半字操作。

    Leakage current reduction system and method
    7.
    发明授权
    Leakage current reduction system and method 有权
    漏电流减少系统及方法

    公开(公告)号：US07237163B2

    公开(公告)日：2007-06-26

    申请号：US10982111

    申请日：2004-11-05

    申请人： Sang Hoo Dhong ,  Hwa-Joon Oh ,  Silvia Melitta Mueller ,  Joel Silberman

    发明人： Sang Hoo Dhong ,  Hwa-Joon Oh ,  Silvia Melitta Mueller ,  Joel Silberman

    IPC分类号： G01R31/28

    CPC分类号： G06F11/267 ,  G01R31/3008

    摘要： An apparatus, a method and a computer program are provided to reduce leakage current in a processor. Traditionally, extra logic is employed to reduce leakage currents. However, reducing leakage current without sacrificing fine grain operations and speed can be difficult. Achieving such a goal can be accomplished by incorporating a multiplexer (mux) into the scan-in path of scan registers so that units or sub-units of the processor can be powered down individually. Additionally, the muxes are not incorporated into time paths, so speed can be preserved.

    摘要翻译： 提供了一种装置，方法和计算机程序以减少处理器中的泄漏电流。 传统上，采用额外的逻辑来减少漏电流。 然而，减少泄漏电流而不牺牲精细的晶粒操作和速度可能是困难的。 可以通过将多路复用器（多路复用器）复用到扫描寄存器的扫描路径中来实现这一目标，从而可以单独关闭处理器的单元或子单元。 此外，多路复用器并不并入时间路径，因此可以保留速度。

    High speed adder design for a multiply-add based floating point unit
    8.
    发明授权
    High speed adder design for a multiply-add based floating point unit 失效
    用于基于加法的浮点单元的高速加法器设计

    公开(公告)号：US08131795B2

    公开(公告)日：2012-03-06

    申请号：US12323257

    申请日：2008-11-25

    申请人： Sang Hoo Dhong ,  Silvia Melitta Mueller ,  Hwa-Joon Oh

    发明人： Sang Hoo Dhong ,  Silvia Melitta Mueller ,  Hwa-Joon Oh

    IPC分类号： G06F7/42 ,  G06F7/38

    CPC分类号： G06F7/483 ,  G06F7/5443

    摘要： A method is provided for improving a high-speed adder for Floating-Point Units (FPU) in a given computer system. The improved adder utilizes a compound incrementer, a compound adder, a carry network, an adder control/selector, and series of multiplexers (muxes). The carry network performs the end-around-carry function simultaneously to and independent of other required functions optimizing the functioning of the adder. Also, the use of a minimum number of muxes is also utilized to reduce mux delays.

    摘要翻译： 提供了一种用于在给定计算机系统中改进浮点单元（FPU）的高速加法器的方法。 改进的加法器利用复合增量器，复合加法器，进位网络，加法器控制/选择器和多路复用器（多路复用器）系列。 进位网络同时执行结束进位功能并且独立于优化加法器功能的其他所需功能。 此外，还使用最小数量的多路复用器来减少多路复用器延迟。

    HIGH SPEED ADDER DESIGN FOR A MULTIPLY-ADD BASED FLOATING POINT UNIT
    9.
    发明申请
    HIGH SPEED ADDER DESIGN FOR A MULTIPLY-ADD BASED FLOATING POINT UNIT 失效
    用于基于多媒体增量浮动点单元的高速加法器设计

    公开(公告)号：US20090077155A1

    公开(公告)日：2009-03-19

    申请号：US12323257

    申请日：2008-11-25

    申请人： Sang Hoo Dhong ,  Silvia Melitta Mueller ,  Hwa-Joon Oh

    发明人： Sang Hoo Dhong ,  Silvia Melitta Mueller ,  Hwa-Joon Oh

    IPC分类号： G06F7/50

    CPC分类号： G06F7/483 ,  G06F7/5443

    摘要： A method is provided for improving a high-speed adder for Floating-Point Units (FPU) in a given computer system. The improved adder utilizes a compound incrementer, a compound adder, a carry network, an adder control/selector, and series of multiplexers (muxes). The carry network performs the end-around-carry function simultaneously to and independent of other required functions optimizing the functioning of the adder. Also, the use of a minimum number of muxes is also utilized to reduce mux delays.

    摘要翻译： 提供了一种用于在给定计算机系统中改进浮点单元（FPU）的高速加法器的方法。 改进的加法器利用复合增量器，复合加法器，进位网络，加法器控制/选择器和多路复用器（多路复用器）系列。 进位网络同时执行终结进位功能，并且独立于优化加法器功能的其他所需功能。 此外，还使用最小数量的多路复用器来减少多路复用器延迟。

    Protecting one-hot logic against short-circuits during power-on
    10.
    发明授权
    Protecting one-hot logic against short-circuits during power-on 失效
    保护开机时防止短路的单热逻辑

    公开(公告)号：US07245159B2

    公开(公告)日：2007-07-17

    申请号：US10891771

    申请日：2004-07-15

    申请人： Sang Hoo Dhong ,  Christian Jacobi ,  Hwa-Joon Oh ,  Silvia Melitta Mueller

    发明人： Sang Hoo Dhong ,  Christian Jacobi ,  Hwa-Joon Oh ,  Silvia Melitta Mueller

    IPC分类号： H03K19/20

    CPC分类号： H03K17/223 ,  H03K17/005

    摘要： A method, a computer program, and an apparatus are provided to protect transmission gates in a multiplexer (mux). Because transmission gates are much faster than the more convention AND-OR arrays, transmission gate usage in muxes are being used more often in high speed circuitry. However, transmission gate have a significant problem in that short circuit are possible for situations where there is not a one-hot select signal. Therefore, to eliminate the problem, logic gates are utilized specifically during Power-On Reset (POR) to force a one-hot selection to prevent any possible short circuits.

    摘要翻译： 提供了一种方法，计算机程序和装置来保护复用器（多路复用器）中的传输门。 因为传输门比更常规的AND-OR阵列快得多，所以在高速电路中更频繁地使用多路复用器中的传输门使用。 然而，传输门具有显着的问题，即在没有单热选择信号的情况下短路是可能的。 因此，为了消除这个问题，在上电复位（POR）期间特别使用逻辑门来强制单热选择以防止任何可能的短路。