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    Hybrid storage device with three-level memory mapping
    1.
    发明授权
    Hybrid storage device with three-level memory mapping 有权

    公开(公告)号：US11630779B2

    公开(公告)日：2023-04-18

    申请号：US17528977

    申请日：2021-11-17

    申请人： Seagate Technology LLC

    发明人： Nitin Satishchandra Kabra ,  Jackson Ellis ,  Niranjan Anant Pol ,  Mark Ish

    IPC分类号： G06F12/0873 ,  G06F12/128 ,  G06F12/02

    摘要： A hybrid storage device with three-level memory mapping is provided. An illustrative device comprises a primary storage device comprising a plurality of primary sub-blocks; a cache memory device comprising a plurality of cache sub-blocks implemented as a cache for the primary storage device; and a controller configured to map at least one portion of one or more primary sub-blocks of the primary storage device stored in the cache to a physical location in the cache memory device using at least one table identifying portions of the primary storage device that are cached in one or more of the cache sub-blocks of the cache memory device, wherein a size of the at least one table is independent of a capacity of the primary storage device.

    Enhanced garbage collection
    2.
    发明授权
    Enhanced garbage collection 有权

    公开(公告)号：US10739996B1

    公开(公告)日：2020-08-11

    申请号：US15213298

    申请日：2016-07-18

    申请人： Seagate Technology LLC

    发明人： David Scott Ebsen ,  Kevin A Gomez ,  Mark Ish ,  Daniel John Benjamin ,  Robert Wayne Moss

    IPC分类号： G06F16/00 ,  G06F3/06 ,  G06F16/17 ,  G06F16/11 ,  G06F16/2455

    摘要： Systems and methods are disclosed for enhanced garbage collection operations at a memory device. The enhanced garbage collection may include selecting data and blocks to garbage collect to improve device performance. Data may be copied and reorganized according to a data stream via which the data was received, or data and blocks may be evaluated for garbage collection based on other access efficiency metrics. Data may be selected for collection based on sequentiality of the data, host access patterns, or other factors. Processing of host commands may be throttled based on a determined amount of work to garbage collect a plurality of blocks, in order to limit variability in host command throughput over a time period.

    LOCKLESS PARITY MANAGEMENT IN A DISTRIBUTED DATA STORAGE SYSTEM
    5.
    发明申请
    LOCKLESS PARITY MANAGEMENT IN A DISTRIBUTED DATA STORAGE SYSTEM 审中-公开

    公开(公告)号：US20170277450A1

    公开(公告)日：2017-09-28

    申请号：US15077420

    申请日：2016-03-22

    申请人： Seagate Technology LLC

    发明人： Mark Ish ,  Anant Baderdinni ,  Balakrishnan Sundararaman ,  Shashank Nemawarkar

    IPC分类号： G06F3/06 ,  G06F12/08

    摘要： Method and apparatus for managing data in a distributed data storage system. In some embodiments, a plurality of storage devices define an overall available memory space. A control circuit stores a first copy of user data from a selected distributed data set in a working set of memory buffers, stores a duplicate, second copy of the user data in an alias set of memory buffers, generates parity data based on the second copy of the user data in the alias set of the memory buffers, and flushes the user data and the parity data from the alias set of memory buffers to the storage devices while the first copy of the user data remains in the working set of the memory buffers. In this way, subsequently received access commands can be serviced using the working set of the memory buffers.

    Low overhead mapping for highly sequential data
    7.
    发明授权
    Low overhead mapping for highly sequential data 有权

    公开(公告)号：US10754555B2

    公开(公告)日：2020-08-25

    申请号：US16201733

    申请日：2018-11-27

    申请人： Seagate Technology LLC

    发明人： Timothy Canepa ,  Jeffrey Munsil ,  Jackson Ellis ,  Mark Ish

    IPC分类号： G06F12/02 ,  G06F3/06

    摘要： Method and apparatus for managing data in a memory, such as a flash memory. A memory module has a non-volatile memory (NVM) and a memory module electronics (MME) circuit configured to program data to and read data from solid-state non-volatile memory cells of the NVM. A map structure associates logical addresses of user data blocks with physical addresses in the NVM at which the user data blocks are stored. A controller circuit arranges the user data blocks into map units (MUs), and directs the MME circuit to write the MUs to a selected page of the NVM. The controller circuit updates the map structure to list only a single occurrence of a physical address for all of the MUs written to the selected page. The map structure is further updated to list an MU offset and an MU length for each of the MUs written to the selected page.

    Active power management
    8.
    发明授权
    Active power management 有权

    公开(公告)号：US10558380B2

    公开(公告)日：2020-02-11

    申请号：US15232682

    申请日：2016-08-09

    申请人： SEAGATE TECHNOLOGY LLC

    发明人： David S. Ebsen ,  Kevin A. Gomez ,  Mark Ish ,  Daniel J. Benjamin

    IPC分类号： G06F3/06

    摘要： Systems and methods for active power management are described. In one embodiment, the systems and methods include obtaining power dissipation metrics for a plurality of components under one or more operating scenarios, generating a reference dissipation model based on the power dissipation metrics of the plurality of components, and implementing the reference dissipation model in a storage system to make component scheduling decisions in relation to power management of the storage system. In some embodiments, the storage system includes any combination of a hard disk drive, a solid state drive, a hybrid drive, and a system of multiple storage drives.

    Managing multiple namespaces in a non-volatile memory (NVM)
    10.
    发明授权
    Managing multiple namespaces in a non-volatile memory (NVM) 有权

    公开(公告)号：US10275361B2

    公开(公告)日：2019-04-30

    申请号：US15609758

    申请日：2017-05-31

    申请人： Seagate Technology LLC

    发明人： Mark Ish ,  Steven S. Williams ,  Jeffrey Munsil

    IPC分类号： G06F12/10

    摘要： Apparatus and method for managing namespaces in a Non-Volatile Memory Express (NVMe) controller environment. A non-volatile memory (NVM) is arranged to store map units (MUs) as addressable data blocks in one or more namespaces. A forward map has a sequence of map unit address (MUA) entries that correlate each of the MUs with the physical locations in the NVM. The MUA entries are grouped into immediately adjacent, contiguous ranges for each of the namespaces. A base MUA array identifies the address, within the forward map, of the beginning MUA entry for each namespace. A new namespace may be added by appending a new range of the MUA entries to the forward map immediate following the last MUA entry, and by adding a new entry to the base MUA array to identify the address, within the forward map, of the beginning MUA entry for the new namespace.