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公开(公告)号：US20220115076A1
公开(公告)日：2022-04-14
申请号：US17499418
申请日：2021-10-12
摘要： A solid-state memory may have many non-individually erasable memory cells arranged into calibration groups with each memory cell in each respective calibration group using a common set of read voltages to sense programmed states. An evaluation circuit of the solid-state memory may be configured to measure at least one read parameter for each calibration group responsive to read operations carried out upon the memory cells in the associated calibration group. An adjustment circuit of the solid-state memory may redistribute the memory cells of an existing calibration group into at least one new calibration group in response to the at least one measured read parameter.
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公开(公告)号：US11923026B2
公开(公告)日：2024-03-05
申请号：US17394738
申请日：2021-08-05
发明人： Jeremy B. Goolsby , Ryan J. Goss , Indrajit Prakash Zagade , Thomas V. Spencer , Jeffrey J. Pream , Christopher A. Smith , Charles McJilton
CPC分类号： G11C29/42 , G06F11/073 , G06F11/0766 , G06F11/3037 , G11C29/12005 , G11C29/18 , G11C29/4401
摘要： A data storage system may connect a non-volatile memory to a quarantine module that generates a quarantine strategy in response to a pending data access request to the non-volatile memory. The quarantine strategy can proactively prescribing a plurality of status levels for physical data addresses of the non-volatile memory. A comparison of a volume of errors for the non-volatile memory to a first threshold of the quarantine strategy with the quarantine module may prompt the alteration of a first status level of the plurality of status levels for a first physical data address of the non-volatile memory, as directed by the quarantine strategy.
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公开(公告)号：US11810625B2
公开(公告)日：2023-11-07
申请号：US17499418
申请日：2021-10-12
CPC分类号： G11C16/26 , G11C29/38 , G11C16/0483
摘要： A solid-state memory may have many non-individually erasable memory cells arranged into calibration groups with each memory cell in each respective calibration group using a common set of read voltages to sense programmed states. An evaluation circuit of the solid-state memory may be configured to measure at least one read parameter for each calibration group responsive to read operations carried out upon the memory cells in the associated calibration group. An adjustment circuit of the solid-state memory may redistribute the memory cells of an existing calibration group into at least one new calibration group in response to the at least one measured read parameter.
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