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公开(公告)号：US20220129378A1
公开(公告)日：2022-04-28
申请号：US17492918
申请日：2021-10-04
IPC分类号： G06F12/02
摘要： Method and apparatus for managing data in a storage device, such as a solid-state drive (SSD). A non-volatile memory (NVM) is arranged into multiple garbage collection units (GCUs) each separately erasable and allocatable as a unit. Read circuitry applies read voltages to memory cells in the GCUs to sense a programmed state of the memory cells. Calibration circuitry groups different memory cells from different GCUs into calibration groups that share a selected set of read voltages. A read command queue accumulates pending read commands to transfer data from the NVM to a local read buffer. Read command coalescing circuitry coalesces selected read commands from the queue into a combined command for execution as a single batch command. The combined batch command may include read voltages for use in retrieval of the requested data.
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公开(公告)号：US11593262B1
公开(公告)日：2023-02-28
申请号：US15962993
申请日：2018-04-25
摘要： Systems and methods are disclosed for the intelligent scheduling of garbage collection operations on a solid state memory. In certain embodiments, a method may comprise initiating a garbage collection process for a solid state memory (SSM) having a multiple die architecture, determining an order of die access for the garbage collection process based on an activity table indicating a use of one or more die in the multiple die architecture, and performing the garbage collection process based on the determined order of die access. Garbage collection reads may be directed to idle die to avoid conflicts with die busy performing other operations, thereby improving system performance.
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公开(公告)号：US10922014B1
公开(公告)日：2021-02-16
申请号：US15997768
申请日：2018-06-05
发明人： Jonathan Henze
IPC分类号： G06F3/06
摘要： Systems and methods are disclosed for die access order variation to a memory having a multiple-die architecture. In certain embodiments, an apparatus may comprise a controller configured to assign a unique die access order to each set of multiple sets of related commands, a die access order controlling an order in which a plurality of dies of a solid state memory are accessed to perform the related commands. A first stream may be assigned a first die access order, and a second stream may be assigned a second, different die access order, thereby distributing the timing of die access collisions between the streams.
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公开(公告)号：US20230032639A1
公开(公告)日：2023-02-02
申请号：US17389521
申请日：2021-07-30
发明人： Jack Vincent Anderson , Jonathan Henze , Ryan James Goss , Charles McJilton , Jeremy Blair Goolsby
摘要： A data storage system may store a first data block having a first data configuration generated by a host in a non-volatile memory that is connected to a data module. A data strategy may be generated with the data module in response to the storage of data with the data strategy consisting of at least one trigger associated with identifying the first data block as hot. The first data block can be replicated to a different memory location with a second data configuration as directed by the data strategy with the first data configuration being different than the second data configuration.
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公开(公告)号：US20220180932A1
公开(公告)日：2022-06-09
申请号：US17541973
申请日：2021-12-03
发明人： Stacey Secatch , David W. Claude , Jonathan Henze
摘要： Method and apparatus for managing data in a non-volatile memory (NVM) of a storage device, such as a solid-state drive (SSD). Data are stored to and retrieved from a group of memory cells in the NVM using a controller circuit. The data are retrieved using a first set of read voltages which are applied to the respective memory cells. The first set of read voltages are accumulated into a history distribution, which is evaluated to arrive at a second set of read voltages based upon characteristics of the history distribution. A calibration operation is performed on the memory cells using the second set of read voltages as a starting point. A final, third set of read voltages is obtained during the calibration operation to provide error rate performance at an acceptable level. The third set of read voltages are thereafter used for subsequent read operations.
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公开(公告)号：US20220115076A1
公开(公告)日：2022-04-14
申请号：US17499418
申请日：2021-10-12
摘要： A solid-state memory may have many non-individually erasable memory cells arranged into calibration groups with each memory cell in each respective calibration group using a common set of read voltages to sense programmed states. An evaluation circuit of the solid-state memory may be configured to measure at least one read parameter for each calibration group responsive to read operations carried out upon the memory cells in the associated calibration group. An adjustment circuit of the solid-state memory may redistribute the memory cells of an existing calibration group into at least one new calibration group in response to the at least one measured read parameter.
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