公开(公告)号：US20160306577A1

公开(公告)日：2016-10-20

申请号：US15196363

申请日：2016-06-29

Applicant: Seagate Technology LLC

Inventor： Timothy Canepa ,  Leonid Baryudin ,  Stephen D. Hanna ,  Alex G. Tang

IPC: G06F3/06 ,  G06F12/08 ,  G06F12/10

CPC classification number: G06F3/0619 ,  G06F3/0608 ,  G06F3/0613 ,  G06F3/064 ,  G06F3/0652 ,  G06F3/0656 ,  G06F3/0658 ,  G06F3/0679 ,  G06F12/0246 ,  G06F12/0802 ,  G06F12/10 ,  G06F2212/1032 ,  G06F2212/1044 ,  G06F2212/214 ,  G06F2212/281 ,  G06F2212/312 ,  G06F2212/7205

Abstract: An apparatus includes a memory and a controller. The memory may be configured to store data. The controller may be configured to process a plurality of input/output requests to read/write to/from the memory. The controller generally includes a processor, a cache and a hardware assist circuit. The processor may be configured to initiate a recycle operation by generation of a start index. The cache may be configured to buffer a first level of a map and less than all of a second level of the map. The hardware assist circuit may be configured to search through the first level or any portions of the second level of the map in the cache in response to the start index, and notify the processor in response to the search detecting one or more blocks in the memory that contain valid data to be recycled.

Abstract translation: 一种装置包括存储器和控制器。 存储器可以被配置为存储数据。 控制器可以被配置为处理多个输入/输出请求以从/从存储器读/写。 控制器通常包括处理器，高速缓存和硬件辅助电路。 处理器可以被配置为通过生成起始索引来启动再循环操作。 缓存可以被配置为缓冲地图的第一级并且小于地图的所有第二级。 硬件辅助电路可以被配置为响应于开始索引来搜索高速缓存中的地图的第二级或第二级的任何部分，并且响应于搜索检测到存储器中的一个或多个块来通知处理器 包含有效数据要循环使用。

公开(公告)号：US09405672B2

公开(公告)日：2016-08-02

申请号：US13941820

申请日：2013-07-15

Applicant: Seagate Technology LLC

Inventor： Timothy Canepa ,  Leonid Baryudin ,  Stephen D. Hanna ,  Alex G. Tang

IPC: G06F12/02

CPC classification number: G06F3/0619 ,  G06F3/0608 ,  G06F3/0613 ,  G06F3/064 ,  G06F3/0652 ,  G06F3/0656 ,  G06F3/0658 ,  G06F3/0679 ,  G06F12/0246 ,  G06F12/0802 ,  G06F12/10 ,  G06F2212/1032 ,  G06F2212/1044 ,  G06F2212/214 ,  G06F2212/281 ,  G06F2212/312 ,  G06F2212/7205

Abstract: An apparatus having a processor and a circuit is disclosed. The processor is generally configured to initiate an operation to recycle a plurality of source blocks in a memory that is nonvolatile. The circuit is generally configured to (i) search through a first of a plurality of levels in a map that defines a plurality of translations between a plurality of logical addresses used at an interface to a computer and a plurality of physical addresses used in the memory and (ii) notify the processor in response to a detection in the first level of one or more of the source blocks to be recycled that contain valid data.

Abstract translation: 公开了一种具有处理器和电路的装置。 处理器通常被配置为发起操作以循环非易失性存储器中的多个源块。 电路通常被配置为（i）搜索在映射中的多个级别中的第一级，所述映射定义在与计算机的接口处使用的多个逻辑地址和在存储器中使用的多个物理地址之间的多个翻译 以及（ii）响应于在第一级中检测到包含有效数据的一个或多个要被回收的源块的检测通知处理器。

公开(公告)号：US10303598B2

公开(公告)日：2019-05-28

申请号：US15196363

申请日：2016-06-29

Applicant: Seagate Technology LLC

Inventor： Timothy Canepa ,  Leonid Baryudin ,  Stephen D. Hanna ,  Alex G. Tang

IPC: G06F12/02 ,  G06F3/06 ,  G06F12/0802 ,  G06F12/10

Abstract: An apparatus includes a memory and a controller. The memory may be configured to store data. The controller may be configured to process a plurality of input/output requests to read/write to/from the memory. The controller generally includes a processor, a cache and a hardware assist circuit. The processor may be configured to initiate a recycle operation by generation of a start index. The cache may be configured to buffer a first level of a map and less than all of a second level of the map. The hardware assist circuit may be configured to search through the first level or any portions of the second level of the map in the cache in response to the start index, and notify the processor in response to the search detecting one or more blocks in the memory that contain valid data to be recycled.

公开(公告)号：US09250995B2

公开(公告)日：2016-02-02

申请号：US13911443

申请日：2013-06-06

Applicant: Seagate Technology LLC

Inventor： Jackson L. Ellis ,  Earl T. Cohen ,  Sivakumar Sambandan ,  Jeonghun Kim ,  Stephen D. Hanna

IPC: G11C29/00 ,  G06F11/10

CPC classification number: G06F11/1016 ,  G06F11/1008 ,  G06F11/1044 ,  G06F11/1076 ,  G11C29/00

Abstract: A method for protecting data in a memory is disclosed. The method generally includes steps (A) to (D). Step (A) converts a logical address of one of a plurality of logical units to a physical address of a corresponding one of a plurality of physical units. Each physical unit is configured to store (i) data from a corresponding one of the logical units, (ii) respective error correction information and (iii) respective verification information. Step (B) writes a particular one of the physical units to the memory. Step (C) reads a portion of the particular physical unit from the memory. The portion includes the respective verification information. The respective verification information includes an indication of the logical address. Step (D) verifies the writing according to the respective verification information in the portion.

Abstract translation: 公开了一种用于保护存储器中的数据的方法。 该方法通常包括步骤（A）至（D）。 步骤（A）将多个逻辑单元中的一个逻辑单元的逻辑地址转换为多个物理单元中相应一个的物理地址。 每个物理单元被配置为存储（i）来自逻辑单元中的相应一个的数据，（ii）各自的纠错信息和（iii）相应的验证信息。 步骤（B）将特定的一个物理单元写入存储器。 步骤（C）从存储器读取特定物理单元的一部分。 该部分包括相应的验证信息。 相应的验证信息包括逻辑地址的指示。 步骤（D）根据该部分中的相应验证信息验证写入。