公开(公告)号：US09058878B2

公开(公告)日：2015-06-16

申请号：US13341303

申请日：2011-12-30

申请人： Seiichi Aritome ,  Soon Ok Seo

发明人： Seiichi Aritome ,  Soon Ok Seo

IPC分类号： G11C16/04 ,  G11C11/56 ,  G11C16/26

CPC分类号： G11C16/0483 ,  G11C11/5642 ,  G11C16/26

摘要： A read method of a semiconductor memory device includes performing a read operation on target cells by using a first read voltage, terminating the read operation on the target cells if, as a result of the read operation on the target cells, error correction is feasible, performing a read operation on first cells next to the target cells along a first direction if, as a result of the read operation on the target cells, error correction is unfeasible, performing the read operation again on the target cells by selecting one of a plurality of read voltages in response to a result of the read operation on the first cells and by using the selected read voltage for reading data of the target cells, and terminating the read operation on the target cells if error correction is feasible.

摘要翻译： 半导体存储器件的读取方法包括通过使用第一读取电压对目标单元执行读取操作，如果作为对目标单元的读取操作的结果，错误校正是可行的，则终止对目标单元的读取操作， 如果作为对目标单元的读取操作的结果，误差校正是不可行的，则对目标单元的旁边的第一单元执行读取操作，通过选择多个目标单元之一对目标单元执行再次操作 的读取电压，并且通过使用所选择的读取电压来读取目标单元的数据，并且如果纠错是可行的，则终止对目标单元的读取操作。

公开(公告)号：US20120163093A1

公开(公告)日：2012-06-28

申请号：US13331820

申请日：2011-12-20

申请人： Seiichi ARITOME ,  Soon Ok Seo

发明人： Seiichi ARITOME ,  Soon Ok Seo

IPC分类号： G11C16/10 ,  G11C16/04

CPC分类号： G11C16/3459 ,  G11C11/5628 ,  G11C16/0483 ,  G11C2211/5621 ,  G11C2211/5642

摘要： A programming method of a nonvolatile memory device includes inputting even data and odd data to be programmed into even memory cells coupled to even bit lines and odd memory cells coupled to odd bit lines, respectively, setting a sense signal as a first sense signal or a second sense signal having a lower voltage level than the first sense signal, based on odd data of odd memory cells adjacent to each of the even memory cells to be programmed, programming the even data into the even memory cells by supplying a program voltage, performing a program verify operation on each of the even memory cells in response to the set sense signal, and programming the odd data into the odd memory cells by supplying a program voltage.

摘要翻译： 非易失性存储器件的编程方法包括：将要编程的偶数数据和奇数数据分别输入耦合到偶位线的偶数存储器单元和耦合到奇数位线的奇数存储单元，将感测信号设置为第一感测信号或 基于与要编程的每个偶数存储器单元相邻的奇数存储器单元的奇数数据，具有比第一感测信号低的电压电平的第二感测信号，通过提供编程电压将偶数数据编程到偶数存储单元中，执行 响应于所设置的感测信号对每个偶数存储单元进行程序验证操作，并通过提供编程电压将奇数数据编程到奇数存储单元中。

公开(公告)号：US08654590B2

公开(公告)日：2014-02-18

申请号：US13331820

申请日：2011-12-20

申请人： Seiichi Aritome ,  Soon Ok Seo

发明人： Seiichi Aritome ,  Soon Ok Seo

IPC分类号： G11C16/34

CPC分类号： G11C16/3459 ,  G11C11/5628 ,  G11C16/0483 ,  G11C2211/5621 ,  G11C2211/5642

摘要： A programming method of a nonvolatile memory device includes inputting even data and odd data to be programmed into even memory cells coupled to even bit lines and odd memory cells coupled to odd bit lines, respectively, setting a sense signal as a first sense signal or a second sense signal having a lower voltage level than the first sense signal, based on odd data of odd memory cells adjacent to each of the even memory cells to be programmed, programming the even data into the even memory cells by supplying a program voltage, performing a program verify operation on each of the even memory cells in response to the set sense signal, and programming the odd data into the odd memory cells by supplying a program voltage.

摘要翻译： 非易失性存储器件的编程方法包括：将要编程的偶数数据和奇数数据分别输入耦合到偶位线的偶数存储器单元和耦合到奇数位线的奇数存储单元，将感测信号设置为第一感测信号或 基于与要编程的每个偶数存储器单元相邻的奇数存储器单元的奇数数据，具有比第一感测信号低的电压电平的第二感测信号，通过提供编程电压将偶数数据编程到偶数存储单元中，执行 响应于所设置的感测信号对每个偶数存储单元进行程序验证操作，并通过提供编程电压将奇数数据编程到奇数存储单元中。

公开(公告)号：US20120170378A1

公开(公告)日：2012-07-05

申请号：US13341303

申请日：2011-12-30

申请人： Seiichi ARITOME ,  Soon Ok Seo

发明人： Seiichi ARITOME ,  Soon Ok Seo

IPC分类号： G11C16/26 ,  G11C16/04

CPC分类号： G11C16/0483 ,  G11C11/5642 ,  G11C16/26

摘要： A read method of a semiconductor memory device includes performing a read operation on target cells by using a first read voltage, terminating the read operation on the target cells if, as a result of the read operation on the target cells, error correction is feasible, performing a read operation on first cells next to the target cells along a first direction if, as a result of the read operation on the target cells, error correction is unfeasible, performing the read operation again on the target cells by selecting one of a plurality of read voltages in response to a result of the read operation on the first cells and by using the selected read voltage for reading data of the target cells, and terminating the read operation on the target cells if error correction is feasible.

摘要翻译： 半导体存储器件的读取方法包括通过使用第一读取电压对目标单元执行读取操作，如果作为对目标单元的读取操作的结果，错误校正是可行的，则终止对目标单元的读取操作， 如果作为对目标单元的读取操作的结果，误差校正是不可行的，则对目标单元的旁边的第一单元执行读取操作，通过选择多个目标单元之一对目标单元执行再次操作 的读取电压，并且通过使用所选择的读取电压来读取目标单元的数据，并且如果纠错是可行的，则终止对目标单元的读取操作。

公开(公告)号：US08759921B2

公开(公告)日：2014-06-24

申请号：US13455504

申请日：2012-04-25

申请人： Soon Ok Seo ,  Sang Bum Lee ,  Se Jun Kim

发明人： Soon Ok Seo ,  Sang Bum Lee ,  Se Jun Kim

IPC分类号： H01L21/70

CPC分类号： H01L29/7926 ,  H01L27/11565 ,  H01L27/11582

摘要： A semiconductor memory device includes a plurality of memory blocks formed over a substrate including source regions and separated from each other by a slit, a plurality of bit lines coupled to the strings of the memory blocks and disposed over the memory blocks, and source contact lines formed within the slits, coupled to the source regions, respectively, and disposed in a direction to cross the plurality of bit lines.

摘要翻译： 半导体存储器件包括形成在包括源极区域并且通过狭缝彼此分离的衬底之上的多个存储器块，耦合到存储块的串并设置在存储器块上的多个位线，以及源极接触线 形成在狭缝内，分别耦合到源极区域，并且设置在与多个位线交叉的方向上。