公开(公告)号：US20240213335A1

公开(公告)日：2024-06-27

申请号：US18288599

申请日：2022-04-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yasuharu HOSAKA ,  Yasutaka NAKAZAWA ,  Takashi SHIRAISHI ,  Rai SATO ,  Kenichi OKAZAKI

IPC: H01L29/417 ,  H01L29/45 ,  H01L29/66 ,  H01L29/786 ,  H10K59/12 ,  H10K59/121

CPC classification number: H01L29/41733 ,  H01L29/66969 ,  H01L29/7869 ,  H10K59/1201 ,  H10K59/1213 ,  H01L29/45

Abstract: A miniaturized semiconductor device is provided. The semiconductor device includes a semiconductor layer over a substrate, a first conductive layer and a second conductive layer being apart from each other over the semiconductor layer, a mask layer in contact with a top surface of the first conductive layer, a first insulating layer covering the semiconductor layer, the first conductive layer, the second conductive layer, and the mask layer, and a third conductive layer overlapping with the semiconductor layer and being over the first insulating layer. The first insulating layer is in contact with a top surface and a side surface of the mask layer, a side surface of the first conductive layer, a top surface and a side surface of the second conductive layer, and a top surface of the semiconductor layer. The semiconductor device includes a region in which the distance between opposite end portions of the first conductive layer and the second conductive layer is less than or equal to 1 μm.

公开(公告)号：US20240057378A1

公开(公告)日：2024-02-15

申请号：US18259287

申请日：2021-12-16

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Daiki NAKAMURA ,  Tomoya AOYAMA ,  Yasutaka NAKAZAWA ,  Rai SATO ,  Seiji YASUMOTO ,  Kiyofumi OGINO ,  Takashi SHIRAISHI

IPC: H10K59/12 ,  H10K59/35 ,  H10K59/38

CPC classification number: H10K59/1201 ,  H10K59/35 ,  H10K59/38 ,  H10K71/233

Abstract: A method for fabricating a display device that easily achieves higher resolution is provided. A display device having both high display quality and high resolution is provided. A first EL film is formed over a first pixel electrode and a second pixel electrode; a first sacrificial film is formed to cover the first EL film; the first sacrificial film and the first EL film are etched to expose the second pixel electrode and to form a first EL layer over the first pixel electrode and a first sacrificial layer over the first EL layer; and the first sacrificial layer is removed. The first EL film and the second EL film are etched by dry etching, and the first sacrificial layer is removed by wet etching.

公开(公告)号：US20240014218A1

公开(公告)日：2024-01-11

申请号：US18035150

申请日：2021-11-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Rai SATO ,  Yasuharu HOSAKA ,  Yasutaka NAKAZAWA ,  Takashi SHIRAISHI ,  Kiyofumi OGINO ,  Kenichi OKAZAKI

IPC: H01L27/12 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L27/1225 ,  H01L29/42384 ,  H01L29/78696 ,  H01L29/7869 ,  H01L27/1288 ,  H01L2029/42388 ,  G02F1/1368

Abstract: A semiconductor device including a transistor with high on-state current and a fabrication method thereof are provided. A semiconductor device having favorable electrical characteristics and a fabrication method thereof are provided. The semiconductor device includes a substrate, an island-shaped insulating layer over the substrate, and a transistor over the substrate and the insulating layer. The transistor includes a gate electrode, a gate insulating layer, a semiconductor layer, and a pair of conductive layers. One of the pair of the conductive layers includes a region overlapping with the insulating layer, and the other of the pair of the conductive layers includes a region not overlapping with the insulating layer. The level of a top surface of the other of the pair of the conductive layers is lower than the level of a top surface of the one of the pair of the conductive layers. Each of the pair of the conductive layers is in contact with the semiconductor layer. The semiconductor layer includes a region overlapping with the gate electrode through the gate insulating layer.

公开(公告)号：US20210399140A1

公开(公告)日：2021-12-23

申请号：US17279153

申请日：2019-09-27

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Rai SATO ,  Masami JINTYOU ,  Masayoshi DOBASHI ,  Takashi SHIRAISHI ,  Satoru SAITO ,  Yasutaka NAKAZAWA

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device with favorable electrical characteristics is provided. A highly reliable semiconductor device is provided. The semiconductor device includes a semiconductor layer, a first insulating layer, a second insulating layer, a metal oxide layer, and a conductive layer; the first insulating layer, the metal oxide layer, and the conductive layer are stacked in this order over the semiconductor layer; an end portion of the first insulating layer is located inward from an end portion of the semiconductor layer; an end portion of the metal oxide layer is located inward from the end portion of the first insulating layer; and an end portion of the conductive layer is located inward from the end portion of the metal oxide layer. The second insulating layer is preferably provided to cover the semiconductor layer, the first insulating layer, the metal oxide layer, and the conductive layer. It is preferable that the semiconductor layer include a first region, a pair of second regions, and a pair of third regions; the first region overlap with the first insulating layer and the metal oxide layer; the second regions between which the first region is sandwiched overlap with the first insulating layer and not overlap with the metal oxide layer; the third regions between which the first region and the pair of second regions are sandwiched not overlap with the first insulating layer; and the third regions be in contact with the second insulating layer.

公开(公告)号：US20210126132A1

公开(公告)日：2021-04-29

申请号：US17257364

申请日：2019-06-26

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Rai SATO ,  Masami JINTYOU ,  Masayoshi DOBASHI ,  Takashi SHIRAISHI

IPC: H01L29/786 ,  G02F1/1362 ,  H01L27/12 ,  H01L29/66

Abstract: A transistor in which shape defects are unlikely to occur is provided. A transistor with favorable electrical characteristics is provided. A semiconductor device with favorable electrical characteristics is provided. The semiconductor device includes a transistor. The transistor includes a semiconductor layer, a first insulating layer, a metal oxide layer, a functional layer, and a conductive layer. The first insulating layer is positioned over the semiconductor layer. The metal oxide layer is positioned over the first insulating layer. The functional layer is positioned over the metal oxide layer. The conductive layer is positioned over the functional layer. The semiconductor layer, the first insulating layer, the metal oxide layer, the functional layer, and the conductive layer have regions overlapping with each other. In the channel length direction of the transistor, end portions of the first insulating layer, the metal oxide layer, the functional layer, and the conductive layer are positioned inward from an end portion of the semiconductor layer. An etching rate of the functional layer with an etchant containing one or more of phosphoric acid, acetic acid, nitric acid, hydrochloric acid, and sulfuric acid is lower than an etching rate of the conductive layer.