利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

42 条记录 (耗时 0.027 秒)

    Junction leakage suppression in memory devices
    2.
    发明授权
    Junction leakage suppression in memory devices 有权
    存储器件中的结漏电抑制

    公开(公告)号：US07939440B2

    公开(公告)日：2011-05-10

    申请号：US11152375

    申请日：2005-06-15

    申请人： Shibly S. Ahmed ,  Jun Kang ,  Hsiao-Han Thio ,  Imran Khan ,  Dong-Hyuk Ju ,  Chuan Lin

    发明人： Shibly S. Ahmed ,  Jun Kang ,  Hsiao-Han Thio ,  Imran Khan ,  Dong-Hyuk Ju ,  Chuan Lin

    IPC分类号： H01L21/425 ,  H01L21/44

    CPC分类号： H01L29/66833 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/7885 ,  H01L29/792

    摘要： A memory device includes a substrate and source and drain regions formed in the substrate. The source and drain regions include both phosphorous and arsenic and the phosphorous may be implanted prior to the arsenic. The memory device also includes a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may further include a second dielectric layer formed over the charge storage element and a control gate formed over the second dielectric layer.

    摘要翻译： 存储器件包括衬底和形成在衬底中的源区和漏区。 源极和漏极区域包括磷和砷，并且磷可以在砷之前被植入。 存储器件还包括形成在衬底上的第一电介质层和形成在第一介电层上的电荷存储元件。 存储器件还可以包括形成在电荷存储元件上的第二电介质层和形成在第二介电层上的控制栅极。

    Junction leakage suppression in memory devices
    3.
    发明申请
    Junction leakage suppression in memory devices 有权
    存储器件中的结漏电抑制

    公开(公告)号：US20070052002A1

    公开(公告)日：2007-03-08

    申请号：US11152375

    申请日：2005-06-15

    申请人： Shibly Ahmed ,  Jun Kang ,  Hsiao-Han Thio ,  Imran Khan ,  Dong-Hyuk Ju ,  Chuan Lin

    发明人： Shibly Ahmed ,  Jun Kang ,  Hsiao-Han Thio ,  Imran Khan ,  Dong-Hyuk Ju ,  Chuan Lin

    IPC分类号： H01L29/788

    CPC分类号： H01L29/66833 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/7885 ,  H01L29/792

    摘要： A memory device includes a substrate and source and drain regions formed in the substrate. The source and drain regions include both phosphorous and arsenic and the phosphorous may be implanted prior to the arsenic. The memory device also includes a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may further include a second dielectric layer formed over the charge storage element and a control gate formed over the second dielectric layer.

    摘要翻译： 存储器件包括衬底和形成在衬底中的源区和漏区。 源极和漏极区域包括磷和砷，并且磷可以在砷之前被植入。 存储器件还包括形成在衬底上的第一电介质层和形成在第一介电层上的电荷存储元件。 存储器件还可以包括形成在电荷存储元件上的第二电介质层和形成在第二介电层上的控制栅极。

    METHOD TO OBTAIN MULTIPLE GATE THICKNESSES USING IN-SITU GATE ETCH MASK APPROACH
    5.
    发明申请
    METHOD TO OBTAIN MULTIPLE GATE THICKNESSES USING IN-SITU GATE ETCH MASK APPROACH 有权
    使用现场浇口掩模方法获取多个浇口厚度的方法

    公开(公告)号：US20080268630A1

    公开(公告)日：2008-10-30

    申请号：US11741998

    申请日：2007-04-30

    申请人： Imran Khan ,  Ahmed Shibly ,  Dong-Hyuk Ju

    发明人： Imran Khan ,  Ahmed Shibly ,  Dong-Hyuk Ju

    IPC分类号： H01L21/3205

    CPC分类号： H01L21/31144 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/82385 ,  H01L21/823857

    摘要： Making gates having multiple thicknesses on the same substrate in a given process flow is provided. For example, a method of making a semiconductor structure having at least two gates of different thickness involves forming a first gate layer having a first thickness; patterning a first hard mask over a portion of the first gate layer to define a first gate underneath the first hard mask having a first gate thickness; forming a second gate layer having a second thickness over the first gate layer and the first hard mask; patterning a second hard mask over a portion of the second gate layer to define a second gate underneath the second hard mask having a second gate thickness; removing portions of the first gate layer and the second gate layer that are not under the first hard mask and the second hard mask; and removing the first hard mask and the second hard mask to provide two gates of different thicknesses.

    摘要翻译： 提供了在给定的工艺流程中在同一基板上制造具有多个厚度的浇口。 例如，制造具有不同厚度的至少两个栅极的半导体结构的方法包括形成具有第一厚度的第一栅极层; 在第一栅极层的一部分上图案化第一硬掩模以限定具有第一栅极厚度的第一硬掩模下面的第一栅极; 在所述第一栅极层和所述第一硬掩模上形成具有第二厚度的第二栅极层; 在第二栅极层的一部分上图案化第二硬掩模以限定具有第二栅极厚度的第二硬掩模下方的第二栅极; 去除不在第一硬掩模下面的第一栅极层和第二栅极层的部分和第二硬掩模; 以及去除第一硬掩模和第二硬掩模以提供不同厚度的两个栅极。

    Apparatus and method for a metal oxide semiconductor field effect transistor with source side punch-through protection implant
    6.
    发明授权
    Apparatus and method for a metal oxide semiconductor field effect transistor with source side punch-through protection implant 有权
    具有源极穿通保护植入物的金属氧化物半导体场效应晶体管的装置和方法

    公开(公告)号：US08530977B1

    公开(公告)日：2013-09-10

    申请号：US10609159

    申请日：2003-06-27

    申请人： Imran Khan ,  Richard M. Fastow ,  Dong-Hyuk Ju

    发明人： Imran Khan ,  Richard M. Fastow ,  Dong-Hyuk Ju

    IPC分类号： H01L29/76 ,  H01L29/94

    CPC分类号： H01L29/66492 ,  H01L21/26586 ,  H01L29/66575 ,  H01L29/66659 ,  H01L29/7835

    摘要： A metal oxide semiconductor field effect transistor (MOSFET) with source side punch-through protection implant. Specifically, the MOSFET comprises a semiconductor substrate, a gate stack formed above the semiconductor substrate, source and drain regions, and a protection implant. The semiconductor substrate comprises a first p-type doping concentration. The source and drain regions comprise an n-type doping concentration, and are formed on opposing sides of the gate stack in the semiconductor substrate. The protection implant comprises a second p-type doping concentration, and is formed in the semiconductor substrate under the source region and surrounds the source region in order to protect the source region from the depletion region corresponding to the drain region.

    摘要翻译： 具有源极穿通保护植入物的金属氧化物半导体场效应晶体管（MOSFET）。 具体地，MOSFET包括半导体衬底，形成在半导体衬底上的栅极堆叠，源极和漏极区域以及保护注入。 半导体衬底包括第一p型掺杂浓度。 源极和漏极区域包括n型掺杂浓度，并且形成在半导体衬底中的栅极堆叠的相对侧上。 保护注入包括第二p型掺杂浓度，并且形成在源极区域下方的半导体衬底中并且围绕源极区域以保护源极区域与对应于漏极区域的耗尽区域保护。

    Method to obtain multiple gate thicknesses using in-situ gate etch mask approach
    7.
    发明授权
    Method to obtain multiple gate thicknesses using in-situ gate etch mask approach 有权
    使用原位栅极蚀刻掩模法获得多个栅极厚度的方法

    公开(公告)号：US07776696B2

    公开(公告)日：2010-08-17

    申请号：US11741998

    申请日：2007-04-30

    申请人： Imran Khan ,  Ahmed Shibly ,  Dong-Hyuk Ju

    发明人： Imran Khan ,  Ahmed Shibly ,  Dong-Hyuk Ju

    IPC分类号： H01L21/8234

    CPC分类号： H01L21/31144 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/82385 ,  H01L21/823857

    摘要： Making gates having multiple thicknesses on the same substrate in a given process flow is provided. For example, a method of making a semiconductor structure having at least two gates of different thickness involves forming a first gate layer having a first thickness; patterning a first hard mask over a portion of the first gate layer to define a first gate underneath the first hard mask having a first gate thickness; forming a second gate layer having a second thickness over the first gate layer and the first hard mask; patterning a second hard mask over a portion of the second gate layer to define a second gate underneath the second hard mask having a second gate thickness; removing portions of the first gate layer and the second gate layer that are not under the first hard mask and the second hard mask; and removing the first hard mask and the second hard mask to provide two gates of different thicknesses.

    摘要翻译： 提供了在给定的工艺流程中在同一基板上制造具有多个厚度的浇口。 例如，制造具有不同厚度的至少两个栅极的半导体结构的方法包括形成具有第一厚度的第一栅极层; 在第一栅极层的一部分上图案化第一硬掩模以限定具有第一栅极厚度的第一硬掩模下面的第一栅极; 在所述第一栅极层和所述第一硬掩模上形成具有第二厚度的第二栅极层; 在第二栅极层的一部分上图案化第二硬掩模以限定具有第二栅极厚度的第二硬掩模下方的第二栅极; 去除不在第一硬掩模下面的第一栅极层和第二栅极层的部分和第二硬掩模; 以及去除第一硬掩模和第二硬掩模以提供不同厚度的两个栅极。

    Semiconductor device having triple LDD structure and lower gate resistance formed with a single implant process
    8.
    发明授权
    Semiconductor device having triple LDD structure and lower gate resistance formed with a single implant process 有权
    半导体器件具有三重LDD结构和较低的栅极电阻，由单一的注入工艺形成

    公开(公告)号：US07084458B1

    公开(公告)日：2006-08-01

    申请号：US11120690

    申请日：2005-05-02

    申请人： Imran Khan ,  Jianshi Wang ,  Yue-Song He ,  Jun Kang

    发明人： Imran Khan ,  Jianshi Wang ,  Yue-Song He ,  Jun Kang

    IPC分类号： H01L29/76

    CPC分类号： H01L29/665 ,  H01L29/66598

    摘要： A method of fabricating a semiconductor device having a triple LDD (lateral diffused dopants) structure is disclosed. This fabrication method requires a single implant process, leading to reduction in fabrication costs and fabrication time. Moreover, this fabrication method increases the surface area of the gate structure of the semiconductor device that is available for silicide to be formed, leading to lower gate resistance.

    摘要翻译： 公开了一种制造具有三重LDD（横向漫射掺杂剂）结构的半导体器件的方法。 这种制造方法需要单个注入工艺，导致制造成本和制造时间的降低。 此外，该制造方法增加可用于要形成的硅化物的半导体器件的栅极结构的表面积，导致较低的栅极电阻。

    Method of fabricating semiconductor device having triple LDD structure and lower gate resistance formed with a single implant process
    9.
    发明授权
    Method of fabricating semiconductor device having triple LDD structure and lower gate resistance formed with a single implant process 失效
    制造具有三重LDD结构的半导体器件的方法和用单个注入工艺形成的较低的栅极电阻

    公开(公告)号：US06939770B1

    公开(公告)日：2005-09-06

    申请号：US10618514

    申请日：2003-07-11

    申请人： Imran Khan ,  Jianshi Wang ,  Yue-Song He ,  Jun Kang

    发明人： Imran Khan ,  Jianshi Wang ,  Yue-Song He ,  Jun Kang

    IPC分类号： H01L21/336

    CPC分类号： H01L29/665 ,  H01L29/66598

    摘要： A method of fabricating a semiconductor device having a triple LDD (lateral diffused dopants) structure is disclosed. This fabrication method requires a single implant process, leading to reduction in fabrication costs and fabrication time. Moreover, this fabrication method increases the surface area of the gate structure of the semiconductor device that is available for silicide to be formed, leading to lower gate resistance.

    摘要翻译： 公开了一种制造具有三重LDD（横向漫射掺杂剂）结构的半导体器件的方法。 这种制造方法需要单个注入工艺，导致制造成本和制造时间的降低。 此外，该制造方法增加可用于要形成的硅化物的半导体器件的栅极结构的表面积，导致较低的栅极电阻。

    SEMANTIC SEARCH METHOD FOR A DISTRIBUTED DATA SYSTEM WITH NUMERICAL TIME SERIES DATA
    10.
    发明申请
    SEMANTIC SEARCH METHOD FOR A DISTRIBUTED DATA SYSTEM WITH NUMERICAL TIME SERIES DATA 审中-公开

    公开(公告)号：US20200334253A1

    公开(公告)日：2020-10-22

    申请号：US16765508

    申请日：2018-11-20

    申请人： Charbel Joseph El Kaed ,  Imran Khan ,  Hicham Hossayni

    发明人： Charbel Joseph El Kaed ,  Imran Khan ,  Hicham Hossayni

    IPC分类号： G06F16/2452 ,  G06F16/36 ,  G06F16/2458 ,  G06F17/18

    摘要： Methods and systems are provided for searching time series information in a distributed data processing system. A method of processing a semantic search query comprises receiving a structured search query, processing the structured search query to deconstruct into query elements, identifying a set of connected elements based on the query elements, processing a time series data structure of the identified set of connected elements to determine a command data element, utilizing the command data element to process the time series data structure of the identified set of connected elements, annotating the time series data structure of each of the identified set of connected elements to form a queried data set, and providing the queried data set.