Junction leakage suppression in memory devices
    5.
    发明申请
    Junction leakage suppression in memory devices 有权
    存储器件中的结漏电抑制

    公开(公告)号:US20070052002A1

    公开(公告)日:2007-03-08

    申请号:US11152375

    申请日:2005-06-15

    IPC分类号: H01L29/788

    摘要: A memory device includes a substrate and source and drain regions formed in the substrate. The source and drain regions include both phosphorous and arsenic and the phosphorous may be implanted prior to the arsenic. The memory device also includes a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may further include a second dielectric layer formed over the charge storage element and a control gate formed over the second dielectric layer.

    摘要翻译: 存储器件包括衬底和形成在衬底中的源区和漏区。 源极和漏极区域包括磷和砷,并且磷可以在砷之前被植入。 存储器件还包括形成在衬底上的第一电介质层和形成在第一介电层上的电荷存储元件。 存储器件还可以包括形成在电荷存储元件上的第二电介质层和形成在第二介电层上的控制栅极。

    VARYING CARRIER MOBILITY IN SEMICONDUCTOR DEVICES TO ACHIEVE OVERALL DESIGN GOALS
    7.
    发明申请
    VARYING CARRIER MOBILITY IN SEMICONDUCTOR DEVICES TO ACHIEVE OVERALL DESIGN GOALS 有权
    半导体设备的变化载体移动实现总体设计目标

    公开(公告)号:US20050029603A1

    公开(公告)日:2005-02-10

    申请号:US10633504

    申请日:2003-08-05

    摘要: A semiconductor device may include a substrate and an insulating layer formed on the substrate. A first device may be formed on the insulating layer, including a first fin. The first fin may be formed on the insulating layer and may have a first fin aspect ratio. A second device may be formed on the insulating layer, including a second fin. The second fin may be formed on the insulating layer and may have a second fin aspect ratio different from the first fin aspect ratio.

    摘要翻译: 半导体器件可以包括衬底和形成在衬底上的绝缘层。 第一器件可以形成在绝缘层上,包括第一鳍片。 第一翅片可以形成在绝缘层上,并且可以具有第一翅片长宽比。 第二装置可以形成在绝缘层上,包括第二鳍片。 第二翅片可以形成在绝缘层上,并且可以具有与第一翅片长宽比不同的第二翅片长宽比。

    Narrow-body damascene tri-gate FinFET
    8.
    发明申请
    Narrow-body damascene tri-gate FinFET 有权
    窄体镶嵌三栅极FinFET

    公开(公告)号:US20050153485A1

    公开(公告)日:2005-07-14

    申请号:US10754540

    申请日:2004-01-12

    摘要: A method of forming a fin field effect transistor includes forming a fin and forming a source region on a first end of the fin and a drain region on a second end of the fin. The method further includes forming a dummy gate with a first semi-conducting material in a first pattern over the fin and forming a dielectric layer around the dummy gate. The method also includes removing the first semi-conducting material to leave a trench in the dielectric layer corresponding to the first pattern, thinning a portion of the fin exposed within the trench, and forming a metal gate within the trench.

    摘要翻译: 形成鳍状场效应晶体管的方法包括:在鳍片的第一端上形成翅片并形成源极区域,在鳍片的第二端部形成漏极区域。 该方法还包括在鳍上形成具有第一图案的第一半导体材料的虚拟栅极,并在虚拟栅极周围形成介电层。 该方法还包括去除第一半导体材料以在对应于第一图案的电介质层中留下沟槽,使在沟槽内暴露的鳍片的一部分变薄,并在沟槽内形成金属栅极。

    Damascene tri-gate FinFET
    9.
    发明申请
    Damascene tri-gate FinFET 有权
    大马士革三栅极FinFET

    公开(公告)号:US20050153492A1

    公开(公告)日:2005-07-14

    申请号:US10754559

    申请日:2004-01-12

    摘要: A method of forming a fin field effect transistor includes forming a fin and forming a source region adjacent a first end of the fin and a drain region adjacent a second end of the fin. The method further includes forming a dummy gate over the fin and forming a dielectric layer around the dummy gate. The method also includes removing the dummy gate to form a trench in the dielectric layer and forming a metal gate in the trench.

    摘要翻译: 形成鳍状场效应晶体管的方法包括形成鳍片并形成与鳍片的第一端相邻的源极区域和与鳍片的第二端部相邻的漏极区域。 该方法还包括在鳍上方形成虚拟栅极,并在虚拟栅极周围形成电介质层。 该方法还包括去除伪栅极以在电介质层中形成沟槽并在沟槽中形成金属栅极。