公开(公告)号：US08530977B1

公开(公告)日：2013-09-10

申请号：US10609159

申请日：2003-06-27

申请人： Imran Khan ,  Richard M. Fastow ,  Dong-Hyuk Ju

发明人： Imran Khan ,  Richard M. Fastow ,  Dong-Hyuk Ju

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L29/66492 ,  H01L21/26586 ,  H01L29/66575 ,  H01L29/66659 ,  H01L29/7835

摘要： A metal oxide semiconductor field effect transistor (MOSFET) with source side punch-through protection implant. Specifically, the MOSFET comprises a semiconductor substrate, a gate stack formed above the semiconductor substrate, source and drain regions, and a protection implant. The semiconductor substrate comprises a first p-type doping concentration. The source and drain regions comprise an n-type doping concentration, and are formed on opposing sides of the gate stack in the semiconductor substrate. The protection implant comprises a second p-type doping concentration, and is formed in the semiconductor substrate under the source region and surrounds the source region in order to protect the source region from the depletion region corresponding to the drain region.

摘要翻译： 具有源极穿通保护植入物的金属氧化物半导体场效应晶体管（MOSFET）。 具体地，MOSFET包括半导体衬底，形成在半导体衬底上的栅极堆叠，源极和漏极区域以及保护注入。 半导体衬底包括第一p型掺杂浓度。 源极和漏极区域包括n型掺杂浓度，并且形成在半导体衬底中的栅极堆叠的相对侧上。 保护注入包括第二p型掺杂浓度，并且形成在源极区域下方的半导体衬底中并且围绕源极区域以保护源极区域与对应于漏极区域的耗尽区域保护。

公开(公告)号：US06897518B1

公开(公告)日：2005-05-24

申请号：US10618191

申请日：2003-07-10

申请人： Sheung Hee Park ,  Richard M. Fastow ,  Dong-Hyuk Ju

发明人： Sheung Hee Park ,  Richard M. Fastow ,  Dong-Hyuk Ju

IPC分类号： H01L21/28 ,  H01L29/423 ,  H01L29/788

CPC分类号： H01L29/42324 ,  H01L21/28273

摘要： A flash memory cell of the present invention comprises a floating gate, having a charge trapping region and a fin region. A source region and a drain region is formed proximate the floating gate. A control gate is formed above the charge trapping region of the floating gate. The fin region advantageously reduces leakage current, thereby allowing further scaling of the cell.

摘要翻译： 本发明的闪存单元包括具有电荷捕获区和鳍区的浮栅。 源极区域和漏极区域形成在浮动栅极附近。 控制栅极形成在浮置栅极的电荷俘获区域的上方。 翅片区域有利地减少泄漏电流，从而允许电池进一步缩放。

公开(公告)号：US07414281B1

公开(公告)日：2008-08-19

申请号：US10658936

申请日：2003-09-09

申请人： Richard M. Fastow ,  Yue-Song He ,  Zhigang Wang

发明人： Richard M. Fastow ,  Yue-Song He ,  Zhigang Wang

IPC分类号： H01L29/76

CPC分类号： H01L29/513 ,  H01L29/7881

摘要： A flash memory cell and a method of forming the same are described. The flash memory cell may include a substrate having a source and a drain, a gate element, and a dielectric layer between the substrate and the gate element. The dielectric layer includes a dielectric material having a dielectric constant that is greater than that of silicon dioxide.

摘要翻译： 描述闪存单元及其形成方法。 闪速存储单元可以包括在衬底和栅极元件之间具有源极和漏极的衬底，栅极元件和介电层。 电介质层包括介电常数大于二氧化硅的电介质材料。

公开(公告)号：US06477083B1

公开(公告)日：2002-11-05

申请号：US09686685

申请日：2000-10-11

申请人： Richard M. Fastow ,  Mark W. Randolph ,  Shane C. Hollmer

发明人： Richard M. Fastow ,  Mark W. Randolph ,  Shane C. Hollmer

IPC分类号： G11C1604

CPC分类号： H01L27/11568 ,  G11C16/0475 ,  G11C16/0491 ,  G11C16/14 ,  H01L27/115

摘要： A bit line selector for a virtual ground non-volatile read only memory (“NROM”) cell array is disclosed. The selector transistors are oriented such that the channel length is perpendicular to the bit line and the channel width is parallel to the bit line. Subsequent reduction in the bit line pitch does not affect the channel width of the select transistors or their drive current.

摘要翻译： 公开了用于虚拟非易失性只读存储器（“NROM”）单元阵列的位线选择器。 选择器晶体管被定向成使得沟道长度垂直于位线并且沟道宽度平行于位线。 位线间距的随后减小不会影响选择晶体管的沟道宽度或其驱动电流。

公开(公告)号：US06819615B1

公开(公告)日：2004-11-16

申请号：US10285909

申请日：2002-10-31

申请人： Richard M. Fastow ,  Wing Han Leung ,  John Wang

发明人： Richard M. Fastow ,  Wing Han Leung ,  John Wang

IPC分类号： G11C702

CPC分类号： G11C16/28 ,  G11C7/14

摘要： A reference cell transistor with a series resistance to improve reliability in reading cells in an associated memory array. The reference cell transistor is coupled in series with a resistive element such that a reference current flows therethrough to reduce a voltage between a gate and a source of the reference cell transistor. This bends the Ids versus Vgate curve of the reference cell downward and compensates for irregularities in the resistance seen in series with the memory cell transistors. In this fashion, the margin when reading memory cells is improved and the reference current is more reliable. The resistive element may be external to a region having the reference cell transistor. Alternatively, the resistive element may be internal to a region with the memory array and reference cell. For example, it may be formed by extending the source region of the reference cell transistor.

摘要翻译： 具有串联电阻的参考单元晶体管，以提高在相关存储器阵列中读取单元的可靠性。 参考单元晶体管与电阻元件串联耦合，使得参考电流流过其中以降低参考单元晶体管的栅极和源极之间的电压。 这将向下弯曲参考单元的Ids与Vgate曲线，并补偿与存储单元晶体管串联看到的电阻的不规则性。 以这种方式，读取存储单元时的余量得到改善，并且参考电流更可靠。 电阻元件可以在具有参考单元晶体管的区域的外部。 或者，电阻元件可以在具有存储器阵列和参考单元的区域内部。 例如，可以通过延长参考单元晶体管的源极区域而形成。

公开(公告)号：US06438031B1

公开(公告)日：2002-08-20

申请号：US09697815

申请日：2000-10-26

申请人： Richard M. Fastow

发明人： Richard M. Fastow

IPC分类号： G11C1604

CPC分类号： G11C16/10 ,  G11C16/0475

摘要： A memory cell that includes a substrate that has a first region and a second region with a channel therebetween. The memory cell further includes a gate above the channel and a charge trapping region that contains a first amount of charge, wherein the first region is doped to such an extent that electric fields are reduced at the locations in the substrate where impact ionization occurs during programming.

摘要翻译： 一种存储单元，其包括具有第一区域的基板和在其间具有通道的第二区域。 存储单元还包括通道上方的栅极和包含第一电荷量的电荷捕获区域，其中第一区域被掺杂到在编程期间发生冲击电离的基板中的位置处的电场减小的程度 。

公开(公告)号：US07217964B1

公开(公告)日：2007-05-15

申请号：US10658937

申请日：2003-09-09

申请人： Richard M. Fastow ,  Kuo-Tung Chang

发明人： Richard M. Fastow ,  Kuo-Tung Chang

IPC分类号： H01L27/10

CPC分类号： H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324

摘要： A method and apparatus for coupling to a source line. Specifically, embodiments of the present invention disclose a memory device comprising an array of flash memory cells with a source line connection that facilitates straight word lines, and a method for producing the same. The array is comprised of a plurality of non-intersecting shallow trench isolation (STI) regions that isolate a plurality of memory cell columns. A source column implanted with n-type dopants is also isolated between an adjoining pair of STI regions. The source column is coupled to a plurality of common source lines that are coupled to a plurality of source regions in the array. A source contact is coupled to the source column for providing electrical coupling with the plurality of source regions. The source contact is located along a row of drain contacts that are coupled to drain regions of a row of memory cells.

摘要翻译： 一种用于耦合到源极线的方法和装置。 具体地，本发明的实施例公开了一种包括具有促进直线字线的源极线连接的闪存单元阵列的存储器件及其制造方法。 阵列由隔离多个存储单元列的多个不相交的浅沟槽隔离（STI）区域组成。 植入n型掺杂剂的源极柱也在相邻的一对STI区域之间隔离。 源极列耦合到耦合到阵列中的多个源极区域的多个公共源极线。 源极触点耦合到源极列，以提供与多个源极区域的电耦合。 源极触点沿着一排漏极触点排列，这些漏极触点被耦合到一行存储器单元的漏极区域。

公开(公告)号：US07142455B1

公开(公告)日：2006-11-28

申请号：US10839562

申请日：2004-05-04

申请人： Sung-Chul Lee ,  Sheung-Hee Park ,  Richard M. Fastow

发明人： Sung-Chul Lee ,  Sheung-Hee Park ,  Richard M. Fastow

IPC分类号： G11C16/04

CPC分类号： G11C11/5635 ,  G11C11/5628 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/349

摘要： A new method for improving the accuracy of read-write operations in a multi-level flash memory cell is disclosed. The method reduces the read margin disturbance caused by the accumulation of holes at a tunneling oxide or tunneling oxide-silicon interface underneath a floating gate of the cell by applying a positive stress to the word line after a program-erase cycle.

摘要翻译： 公开了一种用于提高多级闪存单元中的读写操作的精度的新方法。 该方法通过在编程擦除周期之后向字线施加正应力，减少了在单元的浮动栅极下方的隧道氧化物或隧道氧化物 - 硅界面处的空穴累积引起的读取余量扰动。

公开(公告)号：US06998677B1

公开(公告)日：2006-02-14

申请号：US10795924

申请日：2004-03-08

申请人： Richard M. Fastow

发明人： Richard M. Fastow

IPC分类号： H01L31/113

CPC分类号： H01L27/115 ,  G11C16/0416 ,  H01L27/11568

摘要： A semiconductor component having a memory cell coupled to a trench line and a method for manufacturing the semiconductor component. Trenches having sidewalls are formed in a semiconductor substrate and a trench line is formed in each trench. A polysilicon insert is formed between the trench line and each sidewall of the trench. A column of memory cells is formed between the trenches where each memory cell of the column of memory cells has a gate structure, a source region, and a drain region. The source regions of the column of memory cells are electrically coupled to the trench line on one side of the column of memory cells via one of the polysilicon inserts. The drain regions of the column of memory cells are electrically coupled to the trench line adjacent the opposite side of the column of memory cells via another of the polysilicon inserts.

摘要翻译： 具有耦合到沟槽线的存储单元的半导体部件和用于制造半导体部件的方法。 在半导体衬底中形成具有侧壁的沟槽，并且在每个沟槽中形成沟槽线。 在沟槽线和沟槽的每个侧壁之间形成多晶硅插入物。 在存储单元列的每个存储单元具有栅极结构，源极区和漏极区的沟槽之间形成一列存储单元。 存储单元列的源极区域经由多晶硅插入物之一电耦合到存储器单元列的一侧上的沟槽线。 存储单元列的漏极区域经由多晶硅插入物中的另一个与存储器单元的列的相对侧相邻地沟槽线电耦合。

公开(公告)号：US06961267B1

公开(公告)日：2005-11-01

申请号：US10738301

申请日：2003-12-16

申请人： Richard M. Fastow ,  Lee E. Cleveland ,  Chi Chang

发明人： Richard M. Fastow ,  Lee E. Cleveland ,  Chi Chang

IPC分类号： G11C16/04 ,  G11C16/34

CPC分类号： G11C16/3468

摘要： Accurately programming a memory cell. A voltage is applied to a drain of the memory cell to program the cell. After applying the voltage, the cell is verified as to whether it is programmed to a desired level. The magnitude of the programming voltage is increased and applied to the drain, and the memory cell is re-verified for the desired level. This is repeated until the memory cell is programmed to the desired level. Additional memory cells are programmed in this fashion in order to program multiple memory cells in a narrow distribution around the desired level. The programming can be done one memory cell at a time or many cells can be programmed in parallel. Further a ramped programming voltage can applied to the gate of the memory cell(s), such that the ramped voltage to the gate and the ramped voltage to the drain both program the memory cell.

摘要翻译： 准确编程存储单元。 将电压施加到存储器单元的漏极以对单元进行编程。 在施加电压之后，验证单元是否被编程到所需的电平。 编程电压的大小被增加并施加到漏极，并且存储器单元被重新验证所需的电平。 直到将存储单元编程到所需的电平为止。 以这种方式对附加存储器单元进行编程，以便以围绕期望水平的窄分布来编程多个存储器单元。 编程可以一次完成一个存储单元，或者可以并行编程多个单元。 此外，斜坡编程电压可以施加到存储器单元的栅极，使得到栅极的斜坡电压和到漏极的斜坡电压都对存储器单元进行编程。