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    JUNCTION LEAKAGE SUPPRESSION IN MEMORY DEVICES
    2.
    发明申请
    JUNCTION LEAKAGE SUPPRESSION IN MEMORY DEVICES 有权
    存储器件中的连接泄漏抑制

    公开(公告)号：US20110176363A1

    公开(公告)日：2011-07-21

    申请号：US13074836

    申请日：2011-03-29

    Applicant: Shibly S. AHMED ,  Jun KANG ,  Hsiao-Han THIO ,  Imran KHAN ,  Dong-Hyuk JU ,  Chuan LIN

    Inventor： Shibly S. AHMED ,  Jun KANG ,  Hsiao-Han THIO ,  Imran KHAN ,  Dong-Hyuk JU ,  Chuan LIN

    IPC: G11C16/04 ,  H01L29/788 ,  H01L21/336

    CPC classification number: H01L29/66833 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/7885 ,  H01L29/792

    Abstract: A memory device includes a substrate and source and drain regions formed in the substrate. The source and drain regions include both phosphorous and arsenic and the phosphorous may be implanted prior to the arsenic. The memory device also includes a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may further include a second dielectric layer formed over the charge storage element and a control gate formed over the second dielectric layer.

    Abstract translation: 存储器件包括衬底和形成在衬底中的源区和漏区。 源极和漏极区域包括磷和砷，并且磷可以在砷之前被植入。 存储器件还包括形成在衬底上的第一电介质层和形成在第一介电层上的电荷存储元件。 存储器件还可以包括形成在电荷存储元件上的第二电介质层和形成在第二介电层上的控制栅极。

    Junction leakage suppression in memory devices
    3.
    发明申请
    Junction leakage suppression in memory devices 有权
    存储器件中的结漏电抑制

    公开(公告)号：US20070052002A1

    公开(公告)日：2007-03-08

    申请号：US11152375

    申请日：2005-06-15

    Applicant: Shibly Ahmed ,  Jun Kang ,  Hsiao-Han Thio ,  Imran Khan ,  Dong-Hyuk Ju ,  Chuan Lin

    Inventor： Shibly Ahmed ,  Jun Kang ,  Hsiao-Han Thio ,  Imran Khan ,  Dong-Hyuk Ju ,  Chuan Lin

    IPC: H01L29/788

    CPC classification number: H01L29/66833 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/7885 ,  H01L29/792

    Abstract: A memory device includes a substrate and source and drain regions formed in the substrate. The source and drain regions include both phosphorous and arsenic and the phosphorous may be implanted prior to the arsenic. The memory device also includes a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may further include a second dielectric layer formed over the charge storage element and a control gate formed over the second dielectric layer.

    Abstract translation: 存储器件包括衬底和形成在衬底中的源区和漏区。 源极和漏极区域包括磷和砷，并且磷可以在砷之前被植入。 存储器件还包括形成在衬底上的第一电介质层和形成在第一介电层上的电荷存储元件。 存储器件还可以包括形成在电荷存储元件上的第二电介质层和形成在第二介电层上的控制栅极。

    Using a first liner layer as a spacer in a semiconductor device
    7.
    发明授权
    Using a first liner layer as a spacer in a semiconductor device 有权
    在半导体器件中使用第一衬垫层作为间隔物

    公开(公告)号：US06716710B1

    公开(公告)日：2004-04-06

    申请号：US10126207

    申请日：2002-04-19

    Applicant: Hsiao-Han Thio ,  Nian Yang ,  Zhigang Wang

    Inventor： Hsiao-Han Thio ,  Nian Yang ,  Zhigang Wang

    IPC: H01L21336

    CPC classification number: H01L29/6656 ,  H01L21/76224 ,  H01L21/823468 ,  H01L21/823481

    Abstract: A method of fabricating a semiconductor device. A first layer comprising a first material is deposited to a first thickness on a sidewall of a stacked gate. A second layer comprising a second material is deposited over the first layer. The second layer is deposited without the first layer being etched; hence, the first thickness is unchanged along the sidewall. The second layer is reduced to a second thickness along the sidewall. The first layer and the second layer in combination form a spacer along the sidewall that has a thickness corresponding to the first thickness and the second thickness. Thus, the spacer can be formed using a single etch, reducing the number of processing steps. In addition, the first layer protects shallow trench filler material from gouging during the etch.

    Abstract translation: 一种制造半导体器件的方法。 包括第一材料的第一层在堆叠栅极的侧壁上沉积到第一厚度。 包含第二材料的第二层沉积在第一层上。 沉积第二层，而不蚀刻第一层; 因此，第一厚度沿侧壁不变。 第二层沿着侧壁被还原成第二厚度。 第一层和第二层组合形成沿着侧壁的间隔物，其具有对应于第一厚度和第二厚度的厚度。 因此，间隔物可以使用单一蚀刻形成，减少了处理步骤的数量。 此外，第一层在蚀刻期间保护浅沟槽填料材料免于气刨。

    Method for fabricating devices in core and periphery semiconductor regions using dual spacers
    8.
    发明授权
    Method for fabricating devices in core and periphery semiconductor regions using dual spacers 有权
    使用双间隔物在芯部和外围半导体区域中制造器件的方法

    公开(公告)号：US06670227B1

    公开(公告)日：2003-12-30

    申请号：US10361455

    申请日：2003-02-10

    Applicant: Hsiao-Han Thio ,  Kei-Leong Ho

    Inventor： Hsiao-Han Thio ,  Kei-Leong Ho

    IPC: H01L218238

    CPC classification number: H01L27/11534 ,  H01L21/823418 ,  H01L21/823468 ,  H01L27/105 ,  H01L27/11526 ,  H01L29/6653

    Abstract: For fabricating a first device within a core region and a second device within a periphery region, of a semiconductor substrate, disposable spacers having a first width are formed at sidewalls of a first gate stack of the core region and a second gate stack of the periphery region. Drain and source junctions of the second device are formed in the periphery region to the sides of the disposable spacers of the second gate stack. The disposable spacers are removed and permanent spacers having a second width are formed at the sidewalls of the first and second gate stacks, with the second width being less than the first width. Silicide is formed with an exposed portion of a drain bit line junction within the core region after forming the permanent spacers.

    Abstract translation: 为了在芯区域内的第一器件和周边区域内的第二器件的半导体衬底中制造具有第一宽度的一次性间隔物，形成在芯区域的第一栅极堆叠的侧壁和周边的第二栅极堆叠 地区。 第二器件的漏极和源极结形成在第二栅极堆叠的一次性间隔物的边缘的周边区域中。 去除一次性间隔件，并且在第一和第二栅极堆叠的侧壁处形成具有第二宽度的永久性间隔物，其中第二宽度小于第一宽度。 在形成永久间隔物之后，在芯区域内形成硅化物与漏极位线结的露出部分。

    Dummy gate process to reduce the Vss resistance of flash products
    9.
    发明授权
    Dummy gate process to reduce the Vss resistance of flash products 有权
    虚拟门过程降低闪存产品的Vss电阻

    公开(公告)号：US06461905B1

    公开(公告)日：2002-10-08

    申请号：US10081246

    申请日：2002-02-22

    Applicant: Zhigang Wang ,  Hsiao Han Thio ,  Nian Yang

    Inventor： Zhigang Wang ,  Hsiao Han Thio ,  Nian Yang

    IPC: H01L21338

    CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L29/511

    Abstract: One aspect of the invention relates to a method of manufacturing a flash memory device in which Vss lines are salicided prior to forming memory cell stacks. According to the invention, silicide is aligned to the Vss lines by a layer of temporary material, such as a silicon nitride layer, patterned to form dummy gates. A dielectric layer can be deposited and planarized with the dummy gates prior to their removal. The dielectric layer facilitates selective removal of the dummy gates and formation of memory cell stacks that are properly aligned with the Vss lines and drain regions. The dummy gate concept can be used with methods of forming low resistance Vss lines other than saliciding. One advantage of the invention is that the memory cell stacks are not exposed to high temperature processing used in forming low resistance Vss lines.

    Abstract translation: 本发明的一个方面涉及一种制造闪存器件的方法，其中在形成存储单元堆栈之前，Vss线被浸渍。 根据本发明，硅化物通过图案化以形成伪栅极的诸如氮化硅层的临时材料层与Vss线对准。 介电层可以在其去除之前与虚拟栅极沉积并平坦化。 电介质层有助于选择性地去除伪栅极并形成与Vss线和漏极区正确对准的存储单元堆叠。 虚拟栅极概念可以用于形成除了防水之外的低电阻Vss线的方法。 本发明的一个优点是存储单元堆不暴露于用于形成低电阻Vss线的高温处理。

    Method of protecting a stacked gate structure during fabrication
    10.
    发明授权
    Method of protecting a stacked gate structure during fabrication 有权
    在制造期间保护堆叠栅极结构的方法

    公开(公告)号：US06696331B1

    公开(公告)日：2004-02-24

    申请号：US10217807

    申请日：2002-08-12

    Applicant: Nian Yang ,  Zhigang Wang ,  Hsiao-Han Thio

    Inventor： Nian Yang ,  Zhigang Wang ,  Hsiao-Han Thio

    IPC: H01L218238

    CPC classification number: H01L21/28273 ,  H01L29/42324

    Abstract: A method of protecting a stacked gate structure of a flash memory device during fabrication is disclosed. Additionally, the manner of protecting the stacked gate structure during fabrication is simple to implement and is cost-effective. In particular, a protective layer is deposited on the stacked gate structure to protect the stacked gate structure before a resist removal process is performed a second time. Despite undergoing two resist removal processes, the stacked gate structure suffers less damage than the convention fabrication techniques, increasing the yield and reliability of the flash memory device.

    Abstract translation: 公开了一种在制造期间保护闪存器件的堆叠栅极结构的方法。 此外，在制造期间保护堆叠栅极结构的方式易于实现并且是成本有效的。 特别地，在堆叠的栅极结构上沉积保护层，以在第二次执行抗蚀剂去除处理之前保护堆叠的栅极结构。 尽管经历了两次抗蚀剂去除工艺，堆叠的栅极结构比常规的制造技术遭受的损坏更小，从而提高了闪存器件的产量和可靠性。

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