公开(公告)号：US10734894B1

公开(公告)日：2020-08-04

申请号：US16547107

申请日：2019-08-21

Applicant: Silicon Laboratories Inc.

Inventor： Chao Yang ,  Mohamed Elsayed

IPC: H02M3/07 ,  H02M3/18 ,  G05F1/10 ,  H02M1/44

Abstract: A charge pump system including charge pump circuitry, a charge pump controller, and current limit circuitry. The charge pump circuitry has an input coupled to a supply input node and has an output for developing a drive voltage. The charge pump controller controls the charge pump circuitry to increase the drive voltage above a supply voltage provided to the supply input node. The current limit circuitry limits current through the charge pump circuitry to a limited current level that is less than a maximum current level during a current limit mode to reduce current spikes at the nodes of the charge pump system that may generate EMI. A current mirror may be used as the current limit circuitry to directly limit current through switches of the charge pump circuitry. The timing of the charge pump switches may also be modified such as inserting strategic delays to reduce the current spikes.

公开(公告)号：US10355477B2

公开(公告)日：2019-07-16

申请号：US14927810

申请日：2015-10-30

Applicant: Silicon Laboratories Inc.

Inventor： Mohamed Elsayed ,  Matthew Powell ,  Nicholas M. Atkinson ,  Praveen Kallam

IPC: H02J1/10 ,  G06F1/26 ,  H03K19/0185 ,  G06F1/28 ,  G06F1/30 ,  H02J1/00

Abstract: Circuitry and methods are provided that may be implemented to transfer digital signals between multiple voltage domains while some of these domains may be invalid, e.g., such as to transfer a digital signal from a source voltage domain to a destination voltage domain while the voltage of the source domain is zero or invalid. Possible implementations include, but are not limited to, for power selection and distribution in an integrated circuit chip that has multiple power sources (e.g., such as main power supply and a backup power supply), and in which at startup the chip is agnostic of (or is not aware of) which power supply or power supplies is actually powered and available.

公开(公告)号：US10310528B1

公开(公告)日：2019-06-04

申请号：US15833515

申请日：2017-12-06

Applicant: Silicon Laboratories Inc.

Inventor： Mohamed Elsayed ,  Scott D. Willingham

IPC: G05F1/565 ,  G05F1/46 ,  G05F1/575 ,  G05F3/22 ,  G05F3/24 ,  G05F3/30

Abstract: A band gap circuit with offset voltage error correction including a diode junction circuit, an error amplifier, a current device, a bias current generator, a calibration circuit, and a mode control circuit. During a normal mode of operation, the error amplifier monitors feedback nodes of the diode junction circuit and drives the current device to provide a control current to the diode junction circuit. During a calibration mode, the current device is decoupled from the diode junction circuit and the inputs of the error amplifier are shorted together, the bias generator circuit sinks a bias current from the current device and separately sources a bias current to the diode junction circuit such that the error amplifier operates as a comparator, and the calibration circuit monitors the output of the current device while adjusting a trim current of the error amplifier to minimize an offset voltage error of the error amplifier.

公开(公告)号：US20170126005A1

公开(公告)日：2017-05-04

申请号：US14927810

申请日：2015-10-30

Applicant: Silicon Laboratories Inc.

Inventor： Mohamed Elsayed ,  Matthew Powell ,  Nicholas M. Atkinson ,  Praveen Kallam

IPC: H02J1/10 ,  H03K17/687

CPC classification number: H02J1/10 ,  G06F1/26 ,  G06F1/28 ,  G06F1/305 ,  H02J2001/008 ,  H03K19/0185

Abstract: Circuitry and methods are provided that may be implemented to transfer digital signals between multiple voltage domains while some of these domains may be invalid, e.g., such as to transfer a digital signal from a source voltage domain to a destination voltage domain while the voltage of the source domain is zero or invalid. Possible implementations include, but are not limited to, for power selection and distribution in an integrated circuit chip that has multiple power sources (e.g., such as main power supply and a backup power supply), and in which at startup the chip is agnostic of (or is not aware of) which power supply or power supplies is actually powered and available.