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    CHANNEL CONTROLLING DEVICE FOR IMPROVING DATA READING EFFICIENCY
    1.
    发明申请
    CHANNEL CONTROLLING DEVICE FOR IMPROVING DATA READING EFFICIENCY 有权
    用于提高数据读取效率的信道控制装置

    公开(公告)号：US20170069359A1

    公开(公告)日：2017-03-09

    申请号：US15252227

    申请日：2016-08-31

    Applicant: Silicon Motion Inc.

    Inventor： Chen-Yu Weng ,  Wen-Kai Liu

    IPC: G11C7/10

    CPC classification number: G11C7/1012 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1072 ,  G11C2207/2281

    Abstract: A channel controlling device includes: a multiplexing circuit coupled to a plurality of channels for selecting a specific channel from the channels to output a channel data according to a selecting signal, wherein the channels correspond to a plurality of predetermined digital numbers; a sorting circuit arranged to queue the predetermined digital numbers to form a plurality of queued digital numbers according to a data output order of the channels; and an arbitration circuit, arranged to determine the selecting signal according to the plurality of queued digital numbers.

    Abstract translation: 信道控制装置包括：耦合到多个信道的多路复用电路，用于根据选择信号从信道选择特定信道以输出信道数据，其中信道对应于多个预定数字数字; 排序电路，其被布置成根据所述通道的数据输出顺序排列所述预定数字数字以形成多个排队的数字数字; 以及仲裁电路，被布置为根据所述多个排队的数字数字确定所述选择信号。

    LOW POWER SCHEME FOR BIT FLIPPING LOW DENSITY PARITY CHECK DECODER
    3.
    发明申请
    LOW POWER SCHEME FOR BIT FLIPPING LOW DENSITY PARITY CHECK DECODER 审中-公开

    公开(公告)号：US20170272097A1

    公开(公告)日：2017-09-21

    申请号：US15073606

    申请日：2016-03-17

    Applicant: Silicon Motion Inc.

    Inventor： Chen-Yu Weng

    IPC: H03M13/11

    CPC classification number: H03M13/1108 ,  H03M13/1111 ,  H03M13/3715

    Abstract: A method of power saving for a low-density parity check (LDPC) decoder includes: during each decoding iteration, determining a syndrome weight; and using the determined syndrome weight to set an optimal clock frequency for the LDPC decoding. The LDPC decoding is hard decision hard decoding using a bit-flipping algorithm. When it is determined that the syndrome weights begin to overlap, the method further includes: performing one more iteration in hard decision hard decoding mode; providing a power boost to the LDPC decoder; and switching to hard decision soft decoding mode.

    Low power scheme for bit flipping low density parity check decoder
    4.
    发明授权
    Low power scheme for bit flipping low density parity check decoder 有权

    公开(公告)号：US10050642B2

    公开(公告)日：2018-08-14

    申请号：US15073606

    申请日：2016-03-17

    Applicant: Silicon Motion Inc.

    Inventor： Chen-Yu Weng

    IPC: H03M13/00 ,  H03M13/11

    Abstract: A method of power saving for a low-density parity check (LDPC) decoder includes: during each decoding iteration, determining a syndrome weight; and using the determined syndrome weight to set an optimal clock frequency for the LDPC decoding. The LDPC decoder applies hard decision decoding using a bit-flipping algorithm. When it is determined that the syndrome weights begin to overlap, the method further includes: performing one more iteration in hard decision hard decoding mode; providing a power boost to the LDPC decoder; and switching to hard decision soft decoding mode.

    Channel controlling device for improving data reading efficiency
    5.
    发明授权
    Channel controlling device for improving data reading efficiency 有权

    公开(公告)号：US09704543B2

    公开(公告)日：2017-07-11

    申请号：US15252227

    申请日：2016-08-31

    Applicant: Silicon Motion Inc.

    Inventor： Chen-Yu Weng ,  Wen-Kai Liu

    IPC: G11C7/00 ,  G11C7/10

    CPC classification number: G11C7/1012 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1072 ,  G11C2207/2281

    Abstract: A channel controlling device includes: a multiplexing circuit coupled to a plurality of channels for selecting a specific channel from the channels to output a channel data according to a selecting signal, wherein the channels correspond to a plurality of predetermined digital numbers; a sorting circuit arranged to queue the predetermined digital numbers to form a plurality of queued digital numbers according to a data output order of the channels; and an arbitration circuit, arranged to determine the selecting signal according to the plurality of queued digital numbers.

    LOW POWER SCHEME FOR BIT FLIPPING LOW DENSITY PARITY CHECK DECODER
    7.
    发明申请
    LOW POWER SCHEME FOR BIT FLIPPING LOW DENSITY PARITY CHECK DECODER 审中-公开

    公开(公告)号：US20180331696A1

    公开(公告)日：2018-11-15

    申请号：US16029677

    申请日：2018-07-09

    Applicant: Silicon Motion Inc.

    Inventor： Chen-Yu Weng

    IPC: H03M13/11

    CPC classification number: H03M13/1108 ,  H03M13/1111 ,  H03M13/3715

    Abstract: A method for dynamically adapting a clock frequency used to perform low-density parity check (LDPC) decoding includes: setting a first clock frequency for performing a first LDPC decoding iteration on a received codeword to generate a decoded codeword; performing a successive plurality of LDPC decoding iterations on the decoded codeword; at the end of each LDPC decoding iteration, determining a number of error bits of the decoded codeword and a throughput of the LDPC decoding iteration; and when a number of the error bits increases, increasing the clock frequency for performing a next LDPC decoding iteration so that a throughput of the next LDPC decoding iteration is the same as the throughput of the immediately preceding iteration. The first clock frequency is set according to a number of error bits in an immediately previous decoding operation.

    CHANNEL CONTROLLING DEVICE FOR IMPROVING DATA READING EFFICIENCY
    8.
    发明申请
    CHANNEL CONTROLLING DEVICE FOR IMPROVING DATA READING EFFICIENCY 有权

    公开(公告)号：US20170270980A1

    公开(公告)日：2017-09-21

    申请号：US15605914

    申请日：2017-05-25

    Applicant: Silicon Motion Inc.

    Inventor： Chen-Yu Weng ,  Wen-Kai Liu

    IPC: G11C7/10

    CPC classification number: G11C7/1012 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1072 ,  G11C2207/2281

    Abstract: A channel controlling device includes: a multiplexing circuit coupled to multiple channels for selecting a particular channel from the channels to output a channel data according to a selection signal, wherein the channels correspond to multiple predetermined digital numbers; a sorting circuit arranged to sort the predetermined digital numbers to form multiple sorted digital numbers according to a data output order of the channels; and an arbitration circuit, arranged to determine the selection signal according to the plurality of sorted digital numbers.

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