公开(公告)号：US20190148529A1

公开(公告)日：2019-05-16

申请号：US16245069

申请日：2019-01-10

Applicant: Silicon Storage Technology, Inc.

Inventor： Feng Zhou ,  Xian Liu ,  Chieng-Sheng Su ,  Nhan Do ,  Chunming Wang

IPC: H01L29/66 ,  H01L29/423 ,  H01L21/28 ,  H01L49/02 ,  H01L27/07 ,  H01L29/08 ,  H01L29/788

Abstract: A simplified method for forming pairs of non-volatile memory cells using two polysilicon depositions. A first polysilicon layer is formed on and insulated from the semiconductor substrate in a first polysilicon deposition process. A pair of spaced apart insulation blocks are formed on the first polysilicon layer. Exposed portions of the first poly silicon layer are removed while maintaining a pair of polysilicon blocks of the first polysilicon layer each disposed under one of the pair of insulation blocks. A second polysilicon layer is formed over the substrate and the pair of insulation blocks in a second polysilicon deposition process. Portions of the second polysilicon layer are removed while maintaining a first polysilicon block (disposed between the pair of insulation blocks), a second polysilicon block (disposed adjacent an outer side of one insulation block), and a third polysilicon block (disposed adjacent an outer side of the other insulation block).

公开(公告)号：US09570581B2

公开(公告)日：2017-02-14

申请号：US15091202

申请日：2016-04-05

Applicant: Silicon Storage Technology, Inc.

Inventor： Willem-Jan Toren ,  Xian Liu ,  Gerhard Metzger-Brueckl ,  Nhan Do ,  Stephan Wege ,  Nadia Miridi ,  Chieng-Sheng Su ,  Cecile Bernardi ,  Liz Cuevas ,  Florence Guyot ,  Yueh-Hsin Chen ,  Henry Om'mani ,  Mandana Tadayoni

IPC: H01L29/788 ,  H01L29/66 ,  H01L21/28 ,  H01L27/115 ,  H01L21/762

CPC classification number: H01L29/66545 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/76283 ,  H01L27/11521 ,  H01L27/11568

Abstract: A stack gate structure for a non-volatile memory array has a semiconductor substrate having a plurality of substantially parallel spaced apart active regions, with each active region having an axis in a first direction. A first insulating material is between each stack gate structure in the second direction perpendicular to the first direction. Each stack gate structure has a second insulating material over the active region, a charge holding gate over the second insulating material, a third insulating material over the charge holding gate, and a first portion of a control gate over the third insulating material. A second portion of the control gate is over the first portion of the control gate and over the first insulating material adjacent thereto and extending in the second direction. A fourth insulating material is over the second portion of the control gate.

Abstract translation: 用于非易失性存储器阵列的堆叠栅极结构具有半导体衬底，该半导体衬底具有多个基本上平行的间隔开的有源区，每个有源区具有沿第一方向的轴。 在垂直于第一方向的第二方向上，第一绝缘材料位于每个堆叠栅极结构之间。 每个堆叠栅极结构在有源区域上具有第二绝缘材料，在第二绝缘材料上方的电荷保持栅极，电荷保持栅极上方的第三绝缘材料以及位于第三绝缘材料上的控制栅极的第一部分。 控制栅极的第二部分在控制栅极的第一部分之上，并且与第一部分相邻并且在第二方向上延伸。 第四绝缘材料位于控制栅极的第二部分之上。

公开(公告)号：US20160225878A1

公开(公告)日：2016-08-04

申请号：US15091202

申请日：2016-04-05

Applicant: Silicon Storage Technology, Inc.

Inventor： Willem-Jan Toren ,  Xian Liu ,  Gerhard Metzger-Brueckl ,  Nhan Do ,  Stephan Wege ,  Nadia Miridi ,  Chieng-Sheng Su ,  Cecile Bernardi ,  Liz Cuevas ,  Florence Guyot ,  Yueh-Hsin Chen ,  Henry Om'mani ,  Mandana Tadayoni

IPC: H01L29/66 ,  H01L21/28

CPC classification number: H01L29/66545 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/76283 ,  H01L27/11521 ,  H01L27/11568

Abstract: A stack gate structure for a non-volatile memory array has a semiconductor substrate having a plurality of substantially parallel spaced apart active regions, with each active region having an axis in a first direction. A first insulating material is between each stack gate structure in the second direction perpendicular to the first direction. Each stack gate structure has a second insulating material over the active region, a charge holding gate over the second insulating material, a third insulating material over the charge holding gate, and a first portion of a control gate over the third insulating material. A second portion of the control gate is over the first portion of the control gate and over the first insulating material adjacent thereto and extending in the second direction. A fourth insulating material is over the second portion of the control gate.

Abstract translation: 用于非易失性存储器阵列的堆叠栅极结构具有半导体衬底，该半导体衬底具有多个基本上平行的间隔开的有源区，每个有源区具有沿第一方向的轴。 在垂直于第一方向的第二方向上，第一绝缘材料位于每个堆叠栅极结构之间。 每个堆叠栅极结构在有源区域上具有第二绝缘材料，在第二绝缘材料上方的电荷保持栅极，电荷保持栅极上方的第三绝缘材料以及位于第三绝缘材料上的控制栅极的第一部分。 控制栅极的第二部分在控制栅极的第一部分之上，并且与第一部分相邻并且在第二方向上延伸。 第四绝缘材料位于控制栅极的第二部分之上。