公开(公告)号：US07233166B2

公开(公告)日：2007-06-19

申请号：US10649067

申请日：2003-08-27

申请人： Ruban Kanapathippillai ,  Kumar Ganapathy ,  Thu Nguyen ,  Siva Venkatraman ,  Earle F. Philhower, III ,  Manoj Mehta ,  Kenneth Malich

发明人： Ruban Kanapathippillai ,  Kumar Ganapathy ,  Thu Nguyen ,  Siva Venkatraman ,  Earle F. Philhower, III ,  Manoj Mehta ,  Kenneth Malich

IPC分类号： H03K19/003 ,  H03K17/16 ,  G11C27/02

CPC分类号： G06F1/3203 ,  G06F1/3237 ,  G06F1/3287 ,  G06F9/30072 ,  G06F9/30149 ,  G06F9/30181 ,  G06F9/381 ,  G06F9/382 ,  G06F9/3853 ,  G06F9/3877 ,  Y02D10/128 ,  Y02D10/171 ,  Y02D50/20

摘要： Bus state keepers to maintain a steady state of an inactive bus to conserve power. In one embodiment of the invention, the bus state keepers include a plurality of multiplexers and a plurality of flip flops. The plurality of flip flops to store a state of a bus in response to a select signal.

摘要翻译： 总线状态保持者保持不活动的公共汽车的稳定状态以节省电力。 在本发明的一个实施例中，总线状态保持器包括多个复用器和多个触发器。 多个触发器响应于选择信号来存储总线的状态。

公开(公告)号：US07287148B2

公开(公告)日：2007-10-23

申请号：US10651234

申请日：2003-08-28

申请人： Ruban Kanapathippillai ,  Kumar Ganapathy ,  Thu Nguyen ,  Siva Venkatraman ,  Earle F. Philhower, III ,  Manoj Mehta ,  Kenneth Malich

发明人： Ruban Kanapathippillai ,  Kumar Ganapathy ,  Thu Nguyen ,  Siva Venkatraman ,  Earle F. Philhower, III ,  Manoj Mehta ,  Kenneth Malich

IPC分类号： G06F15/16

CPC分类号： G06F1/3203 ,  G06F1/3237 ,  G06F1/3287 ,  G06F9/30072 ,  G06F9/30149 ,  G06F9/30181 ,  G06F9/381 ,  G06F9/382 ,  G06F9/3853 ,  G06F9/3877 ,  Y02D10/128 ,  Y02D10/171 ,  Y02D50/20

摘要： An integrated circuit comprising a reduced instruction set computer (RISC) controller to execute RISC instructions, one or more digital signal processing (DSP) units to execute DSP instructions, and a unified instruction pipeline coupled to the RISC controller and the one or more DSP units, the unified instruction pipeline to decode and initiate execution of the RISC instructions and the DSP instructions of a unified RISC and DSP instruction set, the unified instruction pipeline to decode and initiate the RISC instructions when the DSP instructions are inactive, and to decode and initiate the DSP instructions when the RISC instructions are inactive.

摘要翻译： 一种集成电路，包括执行RISC指令的简化指令集计算机（RISC）控制器，用于执行DSP指令的一个或多个数字信号处理（DSP）单元，以及耦合到所述RISC控制器和所述一个或多个DSP单元的统一指令流水线 统一指令流水线，用于解码和启动统一RISC和DSP指令集的RISC指令和DSP指令的执行，当DSP指令不活动时，统一指令流水线解码并启动RISC指令，并解码并启动 当RISC指令不活动时，DSP指令。

公开(公告)号：US07490260B2

公开(公告)日：2009-02-10

申请号：US11219008

申请日：2005-09-01

申请人： Siva Venkatraman ,  Earle F. Philhower, III ,  Ruban Kanapathippillai ,  Manoj Mehta

发明人： Siva Venkatraman ,  Earle F. Philhower, III ,  Ruban Kanapathippillai ,  Manoj Mehta

IPC分类号： G06F11/00

CPC分类号： G11C29/76 ,  G11C29/88 ,  G11C29/883

摘要： A reconfigurable memory in an integrated circuit includes an array of memory cells and a memory controller. The array of memory cells in the reconfigurable memory are tested to determine if they are unusable and if so, their associated physical addresses corresponding to their physical location. After determining the physical addresses where any failure exists, the physical addresses locations associated with the physical locations of unusable memory cells or memory blocks are mapped out to avoid addressing them. While mapping out unusable memory locations or memory blocks reduces the total capacity, the reconfigurable memory has sufficient capacity for the integrated circuit to remain functionally usable.

公开(公告)号：US06732203B2

公开(公告)日：2004-05-04

申请号：US10109826

申请日：2002-03-29

申请人： Ruban Kanapathippillai ,  Kumar Ganapathy ,  Thu Nguyen ,  Siva Venkatraman ,  Earle F. Philhower, III ,  Manoj Mehta ,  Kenneth Malich

发明人： Ruban Kanapathippillai ,  Kumar Ganapathy ,  Thu Nguyen ,  Siva Venkatraman ,  Earle F. Philhower, III ,  Manoj Mehta ,  Kenneth Malich

IPC分类号： G06F1338

CPC分类号： G06F1/3203 ,  G06F1/3237 ,  G06F1/3287 ,  G06F9/30072 ,  G06F9/30149 ,  G06F9/30181 ,  G06F9/381 ,  G06F9/382 ,  G06F9/3853 ,  G06F9/3877 ,  Y02D10/128 ,  Y02D10/171 ,  Y02D50/20

摘要： In one embodiment, a bus multiplexer is between a memory and a functional unit of the integrated circuit. An input of the bus multiplexer couples to a global bus having a bit width. A local bus having a lesser bit width couples to an output of the bus multiplexer. The bus multiplexer selectively multiplexes bits of data on the global bus onto bits of the local bus. In another embodiment, an integrated circuit comprises a memory, a global bus, and a functional unit coupled together. The functional unit includes a bus multiplexer with an input coupled to the global bus, and a local bus coupled to an output of the bus multiplexer. The bus width of the local bus is less than that of the global bus. The bus multiplexer selects data from a subset of bits of the global bus to couple onto the bits of the local bus.

摘要翻译： 在一个实施例中，总线复用器位于集成电路的存储器和功能单元之间。 总线多路复用器的输入耦合到具有位宽度的全局总线。 具有较小位宽度的本地总线耦合到总线复用器的输出。 总线复用器有选择地将全局总线上的数据位复用到本地总线的位上。 在另一实施例中，集成电路包括存储器，全局总线和耦合在一起的功能单元。 功能单元包括具有耦合到全局总线的输入的总线复用器和耦合到总线多路复用器的输出的本地总线。 本地总线的总线宽度小于全球总线的总线宽度。 总线复用器从全局总线的位的子集中选择数据以耦合到本地总线的位上。

公开(公告)号：US07318115B2

公开(公告)日：2008-01-08

申请号：US10649090

申请日：2003-08-27

申请人： Ruban Kanapathippillai ,  Kumar Ganapathy ,  Thu Nguyen ,  Siva Venkatraman ,  Earle F. Philhower, III ,  Manoj Mehta ,  Kenneth Malich

发明人： Ruban Kanapathippillai ,  Kumar Ganapathy ,  Thu Nguyen ,  Siva Venkatraman ,  Earle F. Philhower, III ,  Manoj Mehta ,  Kenneth Malich

IPC分类号： G06F12/00

CPC分类号： G06F1/3203 ,  G06F1/3237 ,  G06F1/3287 ,  G06F9/30072 ,  G06F9/30149 ,  G06F9/30181 ,  G06F9/381 ,  G06F9/382 ,  G06F9/3853 ,  G06F9/3877 ,  Y02D10/128 ,  Y02D10/171 ,  Y02D50/20

摘要： Method and apparatus for reducing power consumption in a digital specific signal processor integrated circuit. Data buses are routed through multiplexers to reduce the number of busses routed across an integrated circuit and maintain their prior state. Global memory is clustered into memory clusters. The memory cluster having a memory block to be accessed is activated without activating other memory clusters in the global memory. Inactive data buses retain their state by use of bus state keepers. A loop buffer stores instructions within program loops to avoid memory accesses. Functional blocks can have their clocks gated instruction by instruction to lower power consumption. RISC and DSP units swap circuit activity to reduce power consumption. Local data memory is includes self-timed memory access activation and provides for off boundary access to further lower power consumption.

摘要翻译： 用于降低数字特定信号处理器集成电路中的功耗的方法和装置。 数据总线通过多路复用器布线，以减少跨越集成电路布线的总线数量并保持其先前状态。 全局内存集群到内存集群中。 具有要访问的存储器块的存储器簇被激活而不激活全局存储器中的其他存储器簇。 非活动数据总线通过使用总线状态保持器保持其状态。 循环缓冲器在程序循环中存储指令以避免存储器访问。 功能块可以通过指令使其时钟门控指令降低功耗。 RISC和DSP单元交换电路活动以降低功耗。 本地数据存储器包括自定义存储器访问激活，并提供边界访问以进一步降低功耗。

公开(公告)号：US07502977B2

公开(公告)日：2009-03-10

申请号：US11040954

申请日：2005-01-21

申请人： Siva Venkatraman ,  Earle F. Philhower, III ,  Ruban Kanapathippillai ,  Manoj Mehta

发明人： Siva Venkatraman ,  Earle F. Philhower, III ,  Ruban Kanapathippillai ,  Manoj Mehta

IPC分类号： G11C29/00 ,  G11C5/14 ,  G06F1/26

CPC分类号： G11C29/76 ,  G11C29/88 ,  G11C29/883

摘要： A reconfigurable memory in an integrated circuit includes an array of memory cells and a memory controller. The array of memory cells in the reconfigurable memory are tested to determine if they are unusable and if so, their associated physical addresses corresponding to their physical location. After determining the physical addresses where any failure exists, the physical addresses locations associated with the physical locations of unusable memory cells or memory blocks are mapped out to avoid addressing them. While mapping out unusable memory locations or memory blocks reduces the total capacity, the reconfigurable memory has sufficient capacity for the integrated circuit to remain functionally usable.

公开(公告)号：US07111190B2

公开(公告)日：2006-09-19

申请号：US10056393

申请日：2002-01-24

申请人： Siva Venkatraman ,  Earle F. Philhower, III ,  Ruban Kanapathippillai ,  Manoj Mehta

发明人： Siva Venkatraman ,  Earle F. Philhower, III ,  Ruban Kanapathippillai ,  Manoj Mehta

IPC分类号： G06F11/00

CPC分类号： G11C29/76 ,  G11C29/88 ,  G11C29/883

摘要： A reconfigurable memory in an integrated circuit includes an array of memory cells and a memory controller. The array of memory cells in the reconfigurable memory are tested to determine if they are unusable and if so, their associated physical addresses corresponding to their physical location. After determining the physical addresses where any failure exists, the physical addresses locations associated with the physical locations of unusable memory cells or memory blocks are mapped out to avoid addressing them. While mapping out unusable memory locations or memory blocks reduces the total capacity, the reconfigurable memory has sufficient capacity for the integrated circuit to remain functionally usable.

公开(公告)号：US20130138877A1

公开(公告)日：2013-05-30

申请号：US13754505

申请日：2013-01-30

申请人： Kumar Ganapathy ,  Ruban Kanapathippillai ,  Saurin Shah ,  George Moussa ,  Earle F. Philhower, III ,  Ruchir Shah

发明人： Kumar Ganapathy ,  Ruban Kanapathippillai ,  Saurin Shah ,  George Moussa ,  Earle F. Philhower, III ,  Ruchir Shah

IPC分类号： G11C7/10 ,  G06F12/08

CPC分类号： H04L49/90 ,  G06F12/08 ,  G06F13/28 ,  G06F2213/0038 ,  G11C7/1072

摘要： A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct memory access. The functional modules interface to a systems bus over which the direct memory access occurs. A global buffer memory, to which the direct memory access is desired, is coupled to the system bus. Bus arbitrators are utilized to arbitrate which functional modules have access to the system bus to perform the direct memory access. Once a functional module is selected by the bus arbitrator to have access to the system bus, it can establish a DMA routine with the global buffer memory.

摘要翻译： 在片上系统（SOC）中提供分布式直接存储器访问（DMA）方法，装置和系统。 DMA控制器单元被分配到各种需要直接存储器访问的功能模块。 功能模块与直接存储器访问发生的系统总线接口。 将期望直接存储器访问的全局缓冲存储器耦合到系统总线。 总线仲裁器用于仲裁哪些功能模块可以访问系统总线来执行直接存储器访问。 一旦由总线仲裁器选择功能模块来访问系统总线，它就可以建立与全局缓冲存储器的DMA程序。

公开(公告)号：US07970961B2

公开(公告)日：2011-06-28

申请号：US12268604

申请日：2008-11-11

申请人： Kumar Ganapathy ,  Ruban Kanapathippillai ,  Saurin Shah ,  George Moussa ,  Earle F. Philhower, III ,  Ruchir Shah

发明人： Kumar Ganapathy ,  Ruban Kanapathippillai ,  Saurin Shah ,  George Moussa ,  Earle F. Philhower, III ,  Ruchir Shah

IPC分类号： G06F13/28 ,  G06F12/00 ,  G06F13/36 ,  G06F15/00

CPC分类号： H04L49/90 ,  G06F12/08 ,  G06F13/28 ,  G06F2213/0038 ,  G11C7/1072

摘要： A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct memory access. The functional modules interface to a systems bus over which the direct memory access occurs. A global buffer memory, to which the direct memory access is desired, is coupled to the system bus. Bus arbitrators are utilized to arbitrate which functional modules have access to the system bus to perform the direct memory access. Once a functional module is selected by the bus arbitrator to have access to the system bus, it can establish a DMA routine with the global buffer memory.

摘要翻译： 在片上系统（SOC）中提供分布式直接存储器访问（DMA）方法，装置和系统。 DMA控制器单元被分配到各种需要直接存储器访问的功能模块。 功能模块与直接存储器访问发生的系统总线接口。 将期望直接存储器访问的全局缓冲存储器耦合到系统总线。 总线仲裁器用于仲裁哪些功能模块可以访问系统总线来执行直接存储器访问。 一旦由总线仲裁器选择功能模块来访问系统总线，就可以建立与全局缓冲存储器的DMA程序。

公开(公告)号：US20110320672A1

公开(公告)日：2011-12-29

申请号：US13170493

申请日：2011-06-28

申请人： Kumar Ganapathy ,  Ruban Kanapathippillai ,  Saurin Shah ,  George Moussa ,  Earle F. Philhower, III ,  Ruchir Shah

发明人： Kumar Ganapathy ,  Ruban Kanapathippillai ,  Saurin Shah ,  George Moussa ,  Earle F. Philhower, III ,  Ruchir Shah

IPC分类号： G06F13/28

CPC分类号： H04L49/90 ,  G06F12/08 ,  G06F13/28 ,  G06F2213/0038 ,  G11C7/1072

摘要： A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct memory access. The functional modules interface to a systems bus over which the direct memory access occurs. A global buffer memory, to which the direct memory access is desired, is coupled to the system bus. Bus arbitrators are utilized to arbitrate which functional modules have access to the system bus to perform the direct memory access. Once a functional module is selected by the bus arbitrator to have access to the system bus, it can establish a DMA routine with the global buffer memory.

摘要翻译： 在片上系统（SOC）中提供分布式直接存储器访问（DMA）方法，装置和系统。 DMA控制器单元被分配到各种需要直接存储器访问的功能模块。 功能模块与直接存储器访问发生的系统总线接口。 将期望直接存储器访问的全局缓冲存储器耦合到系统总线。 总线仲裁器用于仲裁哪些功能模块可以访问系统总线来执行直接存储器访问。 一旦由总线仲裁器选择功能模块来访问系统总线，就可以建立与全局缓冲存储器的DMA程序。