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公开(公告)号：US09275330B2
公开(公告)日：2016-03-01
申请号：US13596278
申请日：2012-08-28
CPC分类号： G06N3/04 , G06F9/44505 , G06N3/049 , G06N3/063 , G06N3/088
摘要： Embodiments of the invention provide a neural core circuit comprising a synaptic interconnect network including plural electronic synapses for interconnecting one or more source electronic neurons with one or more target electronic neurons. The interconnect network further includes multiple axon paths and multiple dendrite paths. Each synapse is at a cross-point junction of the interconnect network between a dendrite path and an axon path. The core circuit further comprises a routing module maintaining routing information. The routing module routes output from a source electronic neuron to one or more selected axon paths. Each synapse provides a configurable level of signal conduction from an axon path of a source electronic neuron to a dendrite path of a target electronic neuron.
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公开(公告)号：US20150286924A1
公开(公告)日：2015-10-08
申请号：US13562187
申请日：2012-07-30
摘要： Embodiments of the invention relate to a scalable neural hardware for the noisy-OR model of Bayesian networks. One embodiment comprises a neural core circuit including a pseudo-random number generator for generating random numbers. The neural core circuit further comprises a plurality of incoming electronic axons, a plurality of neural modules, and a plurality of electronic synapses interconnecting the axons to the neural modules. Each synapse interconnects an axon with a neural module. Each neural module receives incoming spikes from interconnected axons. Each neural module represents a noisy-OR gate. Each neural module spikes probabilistically based on at least one random number generated by the pseudo-random number generator unit.
摘要翻译： 本发明的实施例涉及用于贝叶斯网络的噪声-OR模型的可伸缩神经硬件。 一个实施例包括神经核心电路，其包括用于产生随机数的伪随机数发生器。 神经核心电路还包括多个进入的电子轴突，多个神经模块和将轴突与神经模块相互连接的多个电子突触。 每个突触将轴突与神经模块相互连接。 每个神经模块从相互联系的轴突接收进入的尖峰。 每个神经模块表示噪声或门。 每个神经模块基于由伪随机数发生器单元生成的至少一个随机数来概率地尖峰。
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3.发明授权Multi-processor cortical simulations with reciprocal connections with shared weights 有权多处理器皮质模拟与共享权重的互惠连接公开(公告)号：US08924322B2
公开(公告)日：2014-12-30
申请号：US13524798
申请日：2012-06-15
摘要： Embodiments of the invention relate to distributed simulation frameworks that provide reciprocal communication. One embodiment comprises interconnecting neuron groups on different processors via a plurality of reciprocal communication pathways, and facilitating the exchange of reciprocal spiking communication between two different processors using at least one Ineuron module. Each processor includes at least one neuron group. Each neuron group includes at least one electronic neuron.
摘要翻译： 本发明的实施例涉及提供相互通信的分布式仿真框架。 一个实施例包括经由多个相互通信路径在不同处理器上互连神经元组，并且促进使用至少一个Ineuron模块交换两个不同处理器之间的相互加速通信。 每个处理器包括至少一个神经元组。 每个神经元组包括至少一个电子神经元。
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公开(公告)号：US20120109863A1
公开(公告)日：2012-05-03
申请号：US12828091
申请日：2010-06-30
摘要： Embodiments of the invention relate to canonical spiking neurons for spatiotemporal associative memory. An aspect of the invention provides a spatiotemporal associative memory including a plurality of electronic neurons having a layered neural net relationship with directional synaptic connectivity. The plurality of electronic neurons configured to detect the presence of a spatiotemporal pattern in a real-time data stream, and extract the spatiotemporal pattern. The plurality of electronic neurons are further configured to, based on learning rules, store the spatiotemporal pattern in the plurality of electronic neurons, and upon being presented with a version of the spatiotemporal pattern, retrieve the stored spatiotemporal pattern.
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公开(公告)号：US09189729B2
公开(公告)日：2015-11-17
申请号：US13562187
申请日：2012-07-30
摘要： Embodiments of the invention relate to a scalable neural hardware for the noisy-OR model of Bayesian networks. One embodiment comprises a neural core circuit including a pseudo-random number generator for generating random numbers. The neural core circuit further comprises a plurality of incoming electronic axons, a plurality of neural modules, and a plurality of electronic synapses interconnecting the axons to the neural modules. Each synapse interconnects an axon with a neural module. Each neural module receives incoming spikes from interconnected axons. Each neural module represents a noisy-OR gate. Each neural module spikes probabilistically based on at least one random number generated by the pseudo-random number generator unit.
摘要翻译： 本发明的实施例涉及用于贝叶斯网络的噪声-OR模型的可伸缩神经硬件。 一个实施例包括神经核心电路，其包括用于产生随机数的伪随机数发生器。 神经核心电路还包括多个输入电子轴突，多个神经模块以及将轴突与神经模块互连的多个电子突触。 每个突触将轴突与神经模块相互连接。 每个神经模块从相互联系的轴突接收进入的尖峰。 每个神经模块表示噪声或门。 每个神经模块基于由伪随机数发生器单元生成的至少一个随机数来概率地尖峰。
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公开(公告)号：US20150262059A1
公开(公告)日：2015-09-17
申请号：US13596278
申请日：2012-08-28
CPC分类号： G06N3/04 , G06F9/44505 , G06N3/049 , G06N3/063 , G06N3/088
摘要： Embodiments of the invention provide a neural core circuit comprising a synaptic interconnect network including plural electronic synapses for interconnecting one or more source electronic neurons with one or more target electronic neurons. The interconnect network further includes multiple axon paths and multiple dendrite paths. Each synapse is at a cross-point junction of the interconnect network between a dendrite path and an axon path. The core circuit further comprises a routing module maintaining routing information. The routing module routes output from a source electronic neuron to one or more selected axon paths. Each synapse provides a configurable level of signal conduction from an axon path of a source electronic neuron to a dendrite path of a target electronic neuron.
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7.发明授权公开(公告)号：US08898097B2
公开(公告)日：2014-11-25
申请号：US13587594
申请日：2012-08-16
申请人： Bernard V. Brezzo , Leland Chang , Steven K. Esser , Daniel J. Friedman , Yong Liu , Dharmendra S. Modha , Robert K. Montoye , Bipin Rajendran , Jae-sun Seo , Jose A. Tierno
发明人： Bernard V. Brezzo , Leland Chang , Steven K. Esser , Daniel J. Friedman , Yong Liu , Dharmendra S. Modha , Robert K. Montoye , Bipin Rajendran , Jae-sun Seo , Jose A. Tierno
摘要： A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.
摘要翻译： 提供可重构神经网络电路。 可重构神经网络电路包括电子突触阵列，其包括互连多个数字电子神经元的多个突触。 每个神经元包括积分器，其对输入尖峰进行积分，并且当集成输入超过阈值时产生信号。 电路还包括用于重新配置突触阵列的控制模块。 控制模块包括控制电路操作的定时的全局最终状态机，以及允许加标神经元依次访问突触阵列的优先编码器。
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公开(公告)号：US08868477B2
公开(公告)日：2014-10-21
申请号：US13434733
申请日：2012-03-29
CPC分类号： G06N3/04 , G06F9/44505 , G06N3/049 , G06N3/063 , G06N3/088
摘要： Embodiments of the invention provide a neural core circuit comprising a synaptic interconnect network including plural electronic synapses for interconnecting one or more source electronic neurons with one or more target electronic neurons. The interconnect network further includes multiple axon paths and multiple dendrite paths. Each synapse is at a cross-point junction of the interconnect network between a dendrite path and an axon path. The core circuit further comprises a routing module maintaining routing information. The routing module routes output from a source electronic neuron to one or more selected axon paths. Each synapse provides a configurable level of signal conduction from an axon path of a source electronic neuron to a dendrite path of a target electronic neuron.
摘要翻译： 本发明的实施例提供了一种包括突触互连网络的神经核心电路，其包括用于将一个或多个源电子神经元与一个或多个目标电子神经元相互连接的多个电子突触。 互连网络还包括多个轴突路径和多个树枝状路径。 每个突触处于互连网络在树枝状路径和轴突路径之间的交叉点处。 核心电路还包括维护路由信息的路由模块。 路由模块将源电子神经元的输出路由到一个或多个选择的轴突路径。 每个突触提供从源电子神经元的轴突路径到目标电子神经元的枝晶路径的可配置水平的信号传导。
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公开(公告)号：US08856055B2
公开(公告)日：2014-10-07
申请号：US13083414
申请日：2011-04-08
申请人： Bernard V. Brezzo , Leland Chang , Steven K. Esser , Daniel J. Friedman , Yong Liu , Dharmendra S. Modha , Robert K. Montoye , Bipin Rajendran , Jae-sun Seo , Jose A. Tierno
发明人： Bernard V. Brezzo , Leland Chang , Steven K. Esser , Daniel J. Friedman , Yong Liu , Dharmendra S. Modha , Robert K. Montoye , Bipin Rajendran , Jae-sun Seo , Jose A. Tierno
摘要： A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.
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10.发明申请MULTI-PROCESSOR CORTICAL SIMULATIONS WITH RECIPROCAL CONNECTIONS WITH SHARED WEIGHTS 有权具有共享重量的双向连接的多处理器反射模拟公开(公告)号：US20130339281A1
公开(公告)日：2013-12-19
申请号：US13524798
申请日：2012-06-15
IPC分类号： G06N3/04
摘要： Embodiments of the invention relate to distributed simulation frameworks that provide reciprocal communication. One embodiment comprises interconnecting neuron groups on different processors via a plurality of reciprocal communication pathways, and facilitating the exchange of reciprocal spiking communication between two different processors using at least one Ineuron module. Each processor includes at least one neuron group. Each neuron group includes at least one electronic neuron.
摘要翻译： 本发明的实施例涉及提供相互通信的分布式仿真框架。 一个实施例包括经由多个相互通信路径在不同处理器上互连神经元组，并且促进使用至少一个Ineuron模块交换两个不同处理器之间的相互加速通信。 每个处理器包括至少一个神经元组。 每个神经元组包括至少一个电子神经元。
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