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    PRODUCING SPIKE-TIMING DEPENDENT PLASTICITY IN A NEUROMORPHIC NETWORK UTILIZING PHASE CHANGE SYNAPTIC DEVICES
    5.
    发明申请
    PRODUCING SPIKE-TIMING DEPENDENT PLASTICITY IN A NEUROMORPHIC NETWORK UTILIZING PHASE CHANGE SYNAPTIC DEVICES 有权
    在使用相位变化的同步设备的神经网络中生产依赖于时间的相对塑性

    公开(公告)号：US20120084241A1

    公开(公告)日：2012-04-05

    申请号：US12895791

    申请日：2010-09-30

    申请人： Daniel J. Friedman ,  Seongwon Kim ,  Chung H. Lam ,  Dharmendra S. Modha ,  Bipin Rajendran ,  Jose A. Tierno

    发明人： Daniel J. Friedman ,  Seongwon Kim ,  Chung H. Lam ,  Dharmendra S. Modha ,  Bipin Rajendran ,  Jose A. Tierno

    IPC分类号： G06N3/063

    CPC分类号： G06N3/06 ,  G06N3/049 ,  G06N3/063 ,  G06N3/0635 ,  G06N3/08 ,  G11C11/54 ,  G11C13/0004

    摘要： Embodiments of the invention relate to a neuromorphic network for producing spike-timing dependent plasticity. The neuromorphic network includes a plurality of electronic neurons and an interconnect circuit coupled for interconnecting the plurality of electronic neurons. The interconnect circuit includes plural synaptic devices for interconnecting the electronic neurons via axon paths, dendrite paths and membrane paths. Each synaptic device includes a variable state resistor and a transistor device with a gate terminal, a source terminal and a drain terminal, wherein the drain terminal is connected in series with a first terminal of the variable state resistor. The source terminal of the transistor device is connected to an axon path, the gate terminal of the transistor device is connected to a membrane path and a second terminal of the variable state resistor is connected to a dendrite path, such that each synaptic device is coupled between a first axon path and a first dendrite path, and between a first membrane path and said first dendrite path.

    摘要翻译： 本发明的实施例涉及一种用于产生尖峰时序相关可塑性的神经形态网络。 神经元网络包括多个电子神经元和耦合用于互连多个电子神经元的互连电路。 互连电路包括用于经由轴突路径，枝晶路径和膜路径互连电子神经元的多个突触装置。 每个突触装置包括可变状态电阻器和具有栅极端子，源极端子和漏极端子的晶体管器件，其中漏极端子与可变状态电阻器的第一端子串联连接。 晶体管器件的源极端子连接到轴突路径，晶体管器件的栅极端子连接到膜路径，并且可变状态电阻器的第二端子连接到树突路径，使得每个突触器件被耦合 在第一轴突路径和第一枝晶路径之间以及在第一膜路径和所述第一枝晶路径之间。

    Producing spike-timing dependent plasticity in a neuromorphic network utilizing phase change synaptic devices
    6.
    发明授权
    Producing spike-timing dependent plasticity in a neuromorphic network utilizing phase change synaptic devices 有权
    使用相变突触装置在神经元网络中产生尖峰时间依赖性可塑性

    公开(公告)号：US09269042B2

    公开(公告)日：2016-02-23

    申请号：US12895791

    申请日：2010-09-30

    申请人： Daniel J. Friedman ,  Seongwon Kim ,  Chung H. Lam ,  Dharmendra S. Modha ,  Bipin Rajendran ,  Jose A. Tierno

    发明人： Daniel J. Friedman ,  Seongwon Kim ,  Chung H. Lam ,  Dharmendra S. Modha ,  Bipin Rajendran ,  Jose A. Tierno

    IPC分类号： G06N3/063 ,  G06N3/04 ,  G11C11/54 ,  G11C13/00

    CPC分类号： G06N3/06 ,  G06N3/049 ,  G06N3/063 ,  G06N3/0635 ,  G06N3/08 ,  G11C11/54 ,  G11C13/0004

    摘要： Embodiments of the invention relate to a neuromorphic network for producing spike-timing dependent plasticity. The neuromorphic network includes a plurality of electronic neurons and an interconnect circuit coupled for interconnecting the plurality of electronic neurons. The interconnect circuit includes plural synaptic devices for interconnecting the electronic neurons via axon paths, dendrite paths and membrane paths. Each synaptic device includes a variable state resistor and a transistor device with a gate terminal, a source terminal and a drain terminal, wherein the drain terminal is connected in series with a first terminal of the variable state resistor. The source terminal of the transistor device is connected to an axon path, the gate terminal of the transistor device is connected to a membrane path and a second terminal of the variable state resistor is connected to a dendrite path, such that each synaptic device is coupled between a first axon path and a first dendrite path, and between a first membrane path and said first dendrite path.

    摘要翻译： 本发明的实施例涉及一种用于产生尖峰时序相关可塑性的神经形态网络。 神经元网络包括多个电子神经元和耦合用于互连多个电子神经元的互连电路。 互连电路包括用于经由轴突路径，枝晶路径和膜路径互连电子神经元的多个突触装置。 每个突触装置包括可变状态电阻器和具有栅极端子，源极端子和漏极端子的晶体管器件，其中漏极端子与可变状态电阻器的第一端子串联连接。 晶体管器件的源极端子连接到轴突路径，晶体管器件的栅极端子连接到膜路径，并且可变状态电阻器的第二端子连接到树突路径，使得每个突触器件被耦合 在第一轴突路径和第一枝晶路径之间以及在第一膜路径和所述第一枝晶路径之间。

    Sub-rate low-swing data receiver
    7.
    发明授权
    Sub-rate low-swing data receiver 有权
    次速低音数据接收机

    公开(公告)号：US09240789B2

    公开(公告)日：2016-01-19

    申请号：US13600534

    申请日：2012-08-31

    申请人： Daniel J. Friedman ,  Yong Liu ,  Jose A. Tierno

    发明人： Daniel J. Friedman ,  Yong Liu ,  Jose A. Tierno

    IPC分类号： H03K19/0175 ,  H03K19/0185

    CPC分类号： H03K19/018521

    摘要： A receiver is adapted to receive an input signal having a first voltage swing and to generate an output signal having a second voltage swing, the output signal being indicative of the input signal, the second voltage swing being greater than the first voltage swing. The receiver includes a first sub-rate receiver block and at least a second sub-rate receiver block. A receiver clock is divided into a first sub-rate clock phase and at least a second sub-rate clock phase, the first sub-rate clock phase being used to drive the first sub-rate receiver block and the second sub-rate clock phase being used to drive the second sub-rate receiver block. Each of the first sub-rate receiver block and the second sub-rate receiver block includes at least one gated-diode sense amplifier.

    摘要翻译： 接收器适于接收具有第一电压摆幅的输入信号并产生具有第二电压摆幅的输出信号，该输出信号表示输入信号，第二电压摆幅大于第一电压摆幅。 接收机包括第一子速率接收器块和至少第二子速率接收器块。 接收机时钟被分为第一子速率时钟相位和至少第二子速率时钟相位，第一子速率时钟相位用于驱动第一子速率接收机模块和第二子速率时钟相位 用于驱动第二子速率接收器块。 第一子速率接收器块和第二子速率接收器块中的每一个包括至少一个门控二极管读出放大器。

    SUB-RATE LOW-SWING DATA RECEIVER
    8.
    发明申请
    SUB-RATE LOW-SWING DATA RECEIVER 有权
    分数低速数据接收器

    公开(公告)号：US20150303920A1

    公开(公告)日：2015-10-22

    申请号：US13600534

    申请日：2012-08-31

    申请人： Daniel J. Friedman ,  Yong Liu ,  Jose A. Tierno

    发明人： Daniel J. Friedman ,  Yong Liu ,  Jose A. Tierno

    IPC分类号： H03K19/0185

    CPC分类号： H03K19/018521

    摘要： A receiver is adapted to receive an input signal having a first voltage swing and to generate an output signal having a second voltage swing, the output signal being indicative of the input signal, the second voltage swing being greater than the first voltage swing. The receiver includes a first sub-rate receiver block and at least a second sub-rate receiver block. A receiver clock is divided into a first sub-rate clock phase and at least a second sub-rate clock phase, the first sub-rate clock phase being used to drive the first sub-rate receiver block and the second sub-rate clock phase being used to drive the second sub-rate receiver block. Each of the first sub-rate receiver block and the second sub-rate receiver block includes at least one gated-diode sense amplifier.

    摘要翻译： 接收器适于接收具有第一电压摆幅的输入信号并产生具有第二电压摆幅的输出信号，该输出信号表示输入信号，第二电压摆幅大于第一电压摆幅。 接收机包括第一子速率接收器块和至少第二子速率接收器块。 接收机时钟被分为第一子速率时钟相位和至少第二子速率时钟相位，第一子速率时钟相位用于驱动第一子速率接收机模块和第二子速率时钟相位 用于驱动第二子速率接收器块。 第一子速率接收器块和第二子速率接收器块中的每一个包括至少一个门控二极管读出放大器。

    VARACTOR TUNING CONTROL USING REDUNDANT NUMBERING
    9.
    发明申请
    VARACTOR TUNING CONTROL USING REDUNDANT NUMBERING 失效
    使用冗余编号的变频调速控制

    公开(公告)号：US20130076449A1

    公开(公告)日：2013-03-28

    申请号：US13245409

    申请日：2011-09-26

    申请人： Herschel A. Ainspan ,  Daniel J. Friedman ,  Alexander V. Rylyakov ,  Jose A. Tierno

    发明人： Herschel A. Ainspan ,  Daniel J. Friedman ,  Alexander V. Rylyakov ,  Jose A. Tierno

    IPC分类号： H03L7/00

    CPC分类号： H03L7/099 ,  H03L2207/50

    摘要： Techniques for improved tuning control of varactor circuits are disclosed. For example, an apparatus comprises a plurality of varactors for tuning a frequency value. The plurality of varactors comprises approximately sqrt(2N) varactors, where N is a number of tunings steps and the plurality of varactors are respectively sized as 1x, 2x, 3x, 4x, . . . , approximately sqrt(2N)x, and where x is a unit of capacitance. A given one of the N tuning steps may be represented by more than one combination of varactors. This may be referred to as redundant numbering.

    摘要翻译： 公开了用于改进变容二极管电路调谐控制的技术。 例如，一种装置包括用于调谐频率值的多个变容二极管。 多个变容二极管包括大约sqrt（2N）变容二极管，其中N是调谐步骤的数量，并且多个变容二极管分别尺寸为1x，2x，3x，4x。 。 。 ，约为sqrt（2N）x，其中x为电容单位。 N个调谐步骤中的给定一个可以由多个组合的变容二极管表示。 这可以称为冗余编号。