公开(公告)号：US20230386809A1

公开(公告)日：2023-11-30

申请号：US18447557

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Hung TSAI ,  Chin-Szu LEE ,  Szu-Hua WU ,  Jui-Hung HO ,  Chi-Hung LIAO ,  Yu-Jen CHIEN

IPC: H01J37/34 ,  H01L21/285 ,  H01L21/768 ,  C23C14/35 ,  H05K9/00 ,  C23C14/54

CPC classification number: H01J37/3488 ,  H01L21/2855 ,  H01L21/76879 ,  C23C14/35 ,  H01L23/53238 ,  H01J37/3452 ,  H01J37/3476 ,  H05K9/0088 ,  C23C14/54 ,  H01J37/3447

Abstract: A magnetic shield reduces external noise in a chamber including a target and at least one electromagnet for copper physical vapor deposition (PVD). The shield may have a thickness in a range from approximately 0.1 mm to approximately 10 mm to provide sufficient protection from radio frequency and other electromagnetic signals. As a result, copper atoms in the chamber undergo less re-direction from external noise. Additionally, even when hardware failure occurs during PVD (e.g., an electromagnet malfunctions, a wafer stage is not level, and/or a flow optimizer induces too much shift, among other examples), the copper atoms are less susceptible to small re-directions from external noise. As a result, back end of line (BEOL) and/or middle end of line (MEOL) conductive structures are formed in a more uniform manner, which increases conductivity and improves lifetime of an electronic device including the BEOL and/or MEOL conductive structures.

公开(公告)号：US20230380291A1

公开(公告)日：2023-11-23

申请号：US18230358

申请日：2023-08-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yu-Jen CHIEN ,  Jung-Tang Wu ,  Szu-Hua Wu ,  Chin-Szu Lee ,  Meng-Yu Wu

IPC: H10N50/01 ,  H10B61/00 ,  H10N50/80

CPC classification number: H10N50/01 ,  H10B61/22 ,  H10N50/80

Abstract: A method of manufacturing a semiconductor device includes: forming a substrate over the substrate, the substrate defining a logic region and a memory region; depositing a bottom electrode layer across the logic region and the memory region; depositing a magnetic tunnel junction (MTJ) layer over the bottom electrode layer; depositing a first conductive layer over the MTJ layer; depositing a sacrificial layer over the first conductive layer; etching the sacrificial layer in the memory region to expose the first conductive layer in the memory region while keeping the first conductive layer in the logic region covered; depositing a second conductive layer in the memory region and the logic region; patterning the second conductive layer to expose the MTJ layer in the memory region; and etching the patterned second conductive layer and the MTJ layer to form a top electrode and an MTJ, respectively, in the memory region.

公开(公告)号：US20240260479A1

公开(公告)日：2024-08-01

申请号：US18631813

申请日：2024-04-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Jen CHIEN ,  Jung-Tang WU ,  Szu-Hua WU ,  Chin-Szu LEE ,  Meng-Yu WU

IPC: H10N50/01 ,  H10B61/00 ,  H10N50/80

CPC classification number: H10N50/01 ,  H10B61/22 ,  H10N50/80

Abstract: A method of manufacturing a semiconductor device includes: forming a substrate over the substrate, the substrate defining a logic region and a memory region; depositing a bottom electrode layer across the logic region and the memory region; depositing a magnetic tunnel junction (MTJ) layer over the bottom electrode layer; depositing a first conductive layer over the MTJ layer; depositing a sacrificial layer over the first conductive layer; etching the sacrificial layer in the memory region to expose the first conductive layer in the memory region while keeping the first conductive layer in the logic region covered; depositing a second conductive layer in the memory region and the logic region; patterning the second conductive layer to expose the MTJ layer in the memory region; and etching the patterned second conductive layer and the MTJ layer to form a top electrode and an MTJ, respectively, in the memory region.

公开(公告)号：US20230066036A1

公开(公告)日：2023-03-02

申请号：US17461554

申请日：2021-08-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： I-Pin CHIN ,  Yu-Jen CHIEN ,  Chin-Szu LEE

IPC: H01L27/22 ,  C23C16/455 ,  H01L21/67 ,  G11C11/16

Abstract: A method of forming a memory device includes forming a dielectric structure over a wafer. A bottom electrode via is formed in the dielectric structure. A plasma deposition process is performed to deposit a bottom electrode layer over the bottom electrode via and performing the plasma deposition process includes off-axis rotating a magnet over the wafer to control plasma of the plasma deposition process. A memory material layer and a top electrode layer are formed over the bottom electrode layer. The bottom electrode layer, the memory material layer, and the top electrode layer are patterned to respectively form a bottom electrode, a memory layer, and a top electrode.