公开(公告)号：US20200066710A1

公开(公告)日：2020-02-27

申请号：US16666563

申请日：2019-10-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Henry Litzmann EDWARDS ,  Akram A. SALMAN ,  Binghua HU

IPC: H01L27/02 ,  H01L21/265 ,  H01L29/10 ,  H01L29/06 ,  H01L21/762 ,  H01L21/8222 ,  H01L21/763

Abstract: An integrated circuit (IC) includes a semiconductor substrate in which a plurality of spaced-apart deep trench (DT) structures are formed. The IC further includes a plurality of DEEPN diffusion regions, each DEEPN diffusion region surrounding a corresponding one of the DT structures. Each of the DEEPN diffusion regions merges with at least one neighboring DEEPN diffusion region that surrounds at least one neighboring DT structure. The merged DEEPN diffusion regions may partially isolate two electronic devices, e.g. ESD devices.

公开(公告)号：US20220392886A1

公开(公告)日：2022-12-08

申请号：US17887758

申请日：2022-08-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Henry Litzmann EDWARDS ,  Akram A. SALMAN ,  Binghua Hu

IPC: H01L27/02 ,  H01L29/10 ,  H01L29/06 ,  H01L21/265 ,  H01L21/763 ,  H01L21/762 ,  H01L21/8222

Abstract: An ESD cell includes an n+ buried layer (NBL) within a p-epi layer on a substrate. An outer deep trench isolation ring (outer DT ring) includes dielectric sidewalls having a deep n-type diffusion (DEEPN diffusion) ring (DEEPN ring) contacting the dielectric sidewall extending downward to the NBL. The DEEPN ring defines an enclosed p-epi region. A plurality of inner DT structures are within the enclosed p-epi region having dielectric sidewalls and DEEPN diffusions contacting the dielectric sidewalls extending downward from the topside surface to the NBL. The inner DT structures have a sufficiently small spacing with one another so that adjacent DEEPN diffusion regions overlap to form continuous wall of n-type material extending from a first side to a second side of the outer DT ring dividing the enclosed p-epi region into a first and second p-epi region. The first and second p-epi region are connected by the NBL.

公开(公告)号：US20130320396A1

公开(公告)日：2013-12-05

申请号：US13901772

申请日：2013-05-24

Applicant: Texas Instruments Incorporated

Inventor： Akram A. SALMAN ,  Farzan FARBIZ ,  Ann Margaret CONCANNON ,  Gianluca BOSELLI

IPC: H01L27/02

CPC classification number: H01L27/0262 ,  H01L27/0248 ,  H01L27/0259 ,  H01L27/0266 ,  H02H9/046

Abstract: An integrated circuit includes a bidirectional ESD device which has a plurality of parallel switch legs. Each switch leg includes a first current switch and a second current switch in a back-to-back configuration. A first current supply node of each first current switch is coupled to a first terminal of the ESD device. A second current supply node of each second current switch is coupled to a second terminal of the ESD device. A first current collection node of each first current switch is coupled to a second current collection node of the corresponding second current switch. The first current collection nodes in each first current switch is not coupled to any other first current collection node, and similarly, the second current collection node in each instance second current switch is not coupled to any other second current collection node.

Abstract translation: 集成电路包括具有多个平行开关支脚的双向ESD装置。 每个开关支路包括背对背配置中的第一电流开关和第二电流开关。 每个第一电流开关的第一电流供应节点耦合到ESD装置的第一端子。 每个第二电流开关的第二电流供应节点耦合到ESD装置的第二端子。 每个第一电流开关的第一电流采集节点耦合到相应的第二电流开关的第二电流采集节点。 每个第一当前交换机中的第一当前收集节点不耦合到任何其它第一当前收集节点，并且类似地，每个实例中的第二当前收集节点第二当前交换机不耦合到任何其它第二当前收集节点。

公开(公告)号：US20180175021A1

公开(公告)日：2018-06-21

申请号：US15895694

申请日：2018-02-13

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann EDWARDS ,  Akram A. SALMAN ,  Binghua HU

IPC: H01L27/02 ,  H01L29/10 ,  H01L29/06 ,  H01L21/8222 ,  H01L21/265 ,  H01L21/763 ,  H01L21/762 ,  H01L27/06

CPC classification number: H01L27/0259 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/762 ,  H01L21/76237 ,  H01L21/763 ,  H01L21/8222 ,  H01L27/0623 ,  H01L29/06 ,  H01L29/0692 ,  H01L29/10 ,  H01L29/1095

Abstract: An ESD cell includes an n+ buried layer (NBL) within a p-epi layer on a substrate. An outer deep trench isolation ring (outer DT ring) includes dielectric sidewalls having a deep n-type diffusion (DEEPN diffusion) ring (DEEPN ring) contacting the dielectric sidewall extending downward to the NBL. The DEEPN ring defines an enclosed p-epi region. A plurality of inner DT structures are within the enclosed p-epi region having dielectric sidewalls and DEEPN diffusions contacting the dielectric sidewalls extending downward from the topside surface to the NBL. The inner DT structures have a sufficiently small spacing with one another so that adjacent DEEPN diffusion regions overlap to form continuous wall of n-type material extending from a first side to a second side of the outer DT ring dividing the enclosed p-epi region into a first and second p-epi region. The first and second p-epi region are connected by the NBL.

公开(公告)号：US20160163691A1

公开(公告)日：2016-06-09

申请号：US15042233

申请日：2016-02-12

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann EDWARDS ,  Akram A. SALMAN

IPC: H01L27/02 ,  H01L29/66 ,  H01L29/74

CPC classification number: H01L27/0262 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/823892 ,  H01L23/5283 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/66371 ,  H01L29/742

Abstract: An integrated circuit includes an NMOS SCR in which a p-type body well of the NMOS transistor provides a base layer for a vertical NPN layer stack. The base layer is formed by implanting p-type dopants using an implant mask which has a cutout mask element over the base area, so as to block the p-type dopants from the base area. The base layer is implanted concurrently with p-type body wells under NMOS transistors in logic components in the integrated circuit. Subsequent anneals cause the p-type dopants to diffuse into the base area, forming a base with a lower doping density that adjacent regions of the body well of the NMOS transistor in the NMOS SCR. The NMOS SCR may have a symmetric transistor, a drain extended transistor, or may be a bidirectional NMOS SCR with a symmetric transistor integrated with a drain extended transistor.

Abstract translation: 集成电路包括NMOS SCR，其中NMOS晶体管的p型体阱为垂直NPN层堆叠提供基极层。 通过使用在基底区域上具有切口掩模元件的注入掩模注入p型掺杂剂来形成基底层，以便从基底区域阻挡p型掺杂剂。 基极层与集成电路中的逻辑元件中NMOS晶体管的p型体阱同时注入。 随后的退火导致p型掺杂剂扩散到基极区域中，形成具有较低掺杂密度的基极，即在NMOS SCR中的NMOS晶体管的主体阱的相邻区域。 NMOS SCR可以具有对称晶体管，漏极延伸晶体管，或者可以是具有与漏极延伸晶体管集成的对称晶体管的双向NMOS SCR。

公开(公告)号：US20170033096A1

公开(公告)日：2017-02-02

申请号：US15292409

申请日：2016-10-13

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann EDWARDS ,  Akram A. SALMAN

IPC: H01L27/02 ,  H01L21/265 ,  H01L21/8238 ,  H01L21/266 ,  H01L27/092 ,  H01L23/528

CPC classification number: H01L27/0262 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/823892 ,  H01L23/5283 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/66371 ,  H01L29/742

Abstract: An integrated circuit includes an NMOS SCR in which a p-type body well of the NMOS transistor provides a base layer for a vertical NPN layer stack. The base layer is formed by implanting p-type dopants using an implant mask which has a cutout mask element over the base area, so as to block the p-type dopants from the base area. The base layer is implanted concurrently with p-type body wells under NMOS transistors in logic components in the integrated circuit. Subsequent anneals cause the p-type dopants to diffuse into the base area, forming a base with a lower doping density that adjacent regions of the body well of the NMOS transistor in the NMOS SCR. The NMOS SCR may have a symmetric transistor, a drain extended transistor, or may be a bidirectional NMOS SCR with a symmetric transistor integrated with a drain extended transistor.

Abstract translation: 集成电路包括NMOS SCR，其中NMOS晶体管的p型体阱为垂直NPN层堆叠提供基极层。 通过使用在基底区域上具有切口掩模元件的注入掩模注入p型掺杂剂来形成基底层，以便从基底区域阻挡p型掺杂剂。 基极层与集成电路中的逻辑元件中NMOS晶体管的p型体阱同时注入。 随后的退火导致p型掺杂剂扩散到基极区域中，形成具有较低掺杂密度的基极，即在NMOS SCR中的NMOS晶体管的主体阱的相邻区域。 NMOS SCR可以具有对称晶体管，漏极延伸晶体管，或者可以是具有与漏极延伸晶体管集成的对称晶体管的双向NMOS SCR。