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    OPTICAL SENSOR WITH INTEGRATED PINHOLE
    1.
    发明申请
    OPTICAL SENSOR WITH INTEGRATED PINHOLE 审中-公开
    具有集成针孔的光学传感器

    公开(公告)号：US20140203388A1

    公开(公告)日：2014-07-24

    申请号：US14157891

    申请日：2014-01-17

    Applicant: Texas Instruments Incorporated

    Inventor： James BECKER ,  Henry Litzmann EDWARDS

    IPC: H01L31/0232 ,  H01L31/18

    CPC classification number: H01L31/02327 ,  H01L31/02024 ,  H01L31/103

    Abstract: An optical sensor includes a semiconductor substrate having a first conductive type. The optical sensor further includes a photodiode disposed on the semiconductor substrate and a metal layer. The photodiode includes a first semiconductor layer having the first conductive type and a second semiconductor layer, formed on the first semiconductor layer, including a plurality of cathodes having a second conductive type. The first semiconductor layer is configured to collect photocurrent upon reception of incident light. The cathodes are configured to be electrically connected to the first semiconductor layer and the second semiconductor layer is configured to, based on the collected photocurrent, to track the incident light. The metal layer further includes a pinhole configured to collimate the incident light, and the plurality of cathodes form a rotational symmetry of order n with respect to an axis of the pinhole

    Abstract translation: 光学传感器包括具有第一导电类型的半导体衬底。 光学传感器还包括设置在半导体衬底上的光电二极管和金属层。 光电二极管包括具有第一导电类型的第一半导体层和形成在第一半导体层上的第二半导体层，其包括具有第二导电类型的多个阴极。 第一半导体层被配置为在接收到入射光时收集光电流。 阴极被配置为电连接到第一半导体层，并且第二半导体层被配置为基于收集的光电流来跟踪入射光。 金属层还包括被配置为准直入射光的针孔，并且多个阴极相对于针孔的轴线形成n阶的旋转对称

    HYBRID SEMICONDUCTOR DEVICE
    3.
    发明申请
    HYBRID SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20230115019A1

    公开(公告)日：2023-04-13

    申请号：US18066511

    申请日：2022-12-15

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Christopher Boguslaw KOCON ,  Henry Litzmann EDWARDS

    IPC: H01L29/78 ,  H01L29/40 ,  H01L29/417 ,  H01L29/45 ,  H01L29/16 ,  H01L29/20 ,  H01L29/66 ,  H01L29/06

    Abstract: A semiconductor device includes a switch element having a surface and first and second regions and including a first semiconductor material having a band-gap. The first region of the switch element is coupled to a source contact. A floating electrode has first and second ends. The first end of the floating electrode is coupled to the second region of the switch element. A voltage-support structure includes a second semiconductor material having a band-gap that is larger than the band-gap of the first semiconductor material. The voltage-support structure is in contact with the second end of the floating electrode. A drain contact is coupled to the voltage-support structure.

    ISOLATION STRUCTURE FOR IC WITH EPI REGIONS SHARING THE SAME TANK
    7.
    发明申请
    ISOLATION STRUCTURE FOR IC WITH EPI REGIONS SHARING THE SAME TANK 有权

    公开(公告)号：US20220392886A1

    公开(公告)日：2022-12-08

    申请号：US17887758

    申请日：2022-08-15

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Henry Litzmann EDWARDS ,  Akram A. SALMAN ,  Binghua Hu

    IPC: H01L27/02 ,  H01L29/10 ,  H01L29/06 ,  H01L21/265 ,  H01L21/763 ,  H01L21/762 ,  H01L21/8222

    Abstract: An ESD cell includes an n+ buried layer (NBL) within a p-epi layer on a substrate. An outer deep trench isolation ring (outer DT ring) includes dielectric sidewalls having a deep n-type diffusion (DEEPN diffusion) ring (DEEPN ring) contacting the dielectric sidewall extending downward to the NBL. The DEEPN ring defines an enclosed p-epi region. A plurality of inner DT structures are within the enclosed p-epi region having dielectric sidewalls and DEEPN diffusions contacting the dielectric sidewalls extending downward from the topside surface to the NBL. The inner DT structures have a sufficiently small spacing with one another so that adjacent DEEPN diffusion regions overlap to form continuous wall of n-type material extending from a first side to a second side of the outer DT ring dividing the enclosed p-epi region into a first and second p-epi region. The first and second p-epi region are connected by the NBL.

    WAVELENGTH SENSITIVE PHOTODIODE EMPLOYING SHORTED JUNCTION
    8.
    发明申请
    WAVELENGTH SENSITIVE PHOTODIODE EMPLOYING SHORTED JUNCTION 有权
    波长敏感光电子使用短路接头

    公开(公告)号：US20130207211A1

    公开(公告)日：2013-08-15

    申请号：US13768024

    申请日：2013-02-15

    Applicant: Texas Instruments Incorporated

    Inventor： Henry Litzmann EDWARDS ,  Dimitar Trifonov TRIFONOV

    IPC: H01L31/02

    CPC classification number: H01L31/02002 ,  H01L31/022408 ,  H01L31/1013 ,  H01L31/103

    Abstract: A semiconductor device contains a photodiode which has a plurality of p-n junctions disposed in a stack. Two contact structures on the semiconductor device are connected across at least one of the junctions to allow electrical connection to an external detection circuit, so that signal current from incident light on the photodiode which generates electron-hole pairs across the connected junction may be sensed by the external detection circuit. At least one of the junctions is electrically shorted at the semiconductor device, so that signal current from the shorted junction may not be sensed by the external detection circuit.

    Abstract translation: 半导体器件包含具有布置在堆叠中的多个p-n结的光电二极管。 半导体器件上的两个接触结构连接在至少一个结点上，以允许与外部检测电路的电连接，从而在穿过连接的接合点产生电子 - 空穴对的光电二极管上的入射光的信号电流可以被 外部检测电路。 至少一个结点在半导体器件处电气短路，使得来自短路端的信号电流可能不被外部检测电路感测到。

    LOW-CAPACITANCE PHOTODIODE UTILIZING VERTICAL CARRIER CONFINEMENT
    9.
    发明申请
    LOW-CAPACITANCE PHOTODIODE UTILIZING VERTICAL CARRIER CONFINEMENT 有权
    低容量光电子利用垂直载体的限制

    公开(公告)号：US20130207210A1

    公开(公告)日：2013-08-15

    申请号：US13767978

    申请日：2013-02-15

    Applicant: Texas Instruments Incorporated

    Inventor： Henry Litzmann EDWARDS ,  Dimitar Trifonov TRIFONOV

    IPC: H01L31/075 ,  H01L31/0224

    CPC classification number: H01L31/075 ,  H01L31/0224 ,  H01L31/022408 ,  H01L31/103 ,  H01L31/1804 ,  Y02E10/547

    Abstract: A semiconductor device contains a photodiode which includes a buried collection region formed by a bandgap well to vertically confine photo-generated minority carriers. the bandgap well has the same conductivity as the semiconductor material immediately above and below the bandgap well. A net average doping density in the bandgap well is at least a factor of ten less than net average doping densities immediately above and below the bandgap well. A node of the photodiode, either the anode or the cathode, is connected to the buried collection region to collect the minority carriers, the polarity of the node matches the polarity of the minority carriers. The photodiode node connected to the buried collection region occupies less lateral area than the lateral area of the buried collection region.

    Abstract translation: 半导体器件包括光电二极管，其包括由带隙阱形成的掩埋采集区域，以垂直地限制光产生的少数载流子。 带隙阱具有与带隙阱正上方和下方的半导体材料相同的导电性。 带隙阱中的净平均掺杂密度至少比带隙阱上方和下方的净平均掺杂密度小十倍。 光电二极管（阳极或阴极）的一个节点连接到埋藏采集区域以收集少数载流子，节点的极性与少数载流子的极性匹配。 连接到埋藏采集区的光电二极管节点占据比埋藏收集区域的侧向区域更小的横向面积。

    TRANSISTOR DEVICE WITH BUFFERED DRAIN
    10.
    发明申请
    TRANSISTOR DEVICE WITH BUFFERED DRAIN 有权

    公开(公告)号：US20230101691A1

    公开(公告)日：2023-03-30

    申请号：US17489513

    申请日：2021-09-29

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Henry Litzmann EDWARDS

    IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10

    Abstract: A semiconductor device includes a source region. A drain region has a first conductivity type and a second dopant concentration spaced apart from the source region. A first drift region is located between the source region and the drain region and has the first conductivity type and a first dopant concentration that is lower than the second dopant concentration of the drain region. An oxide structure includes a first portion on or over the first drift region and a tapered portion between the first portion and the drain region. A substrate surface extension is between the tapered portion and the drain region. A buffer region has the first conductivity type between the first drift region and the drain region and under the tapered portion of the oxide structure. The buffer region has a third dopant concentration between the second dopant concentration and the first dopant concentration.

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